Electric lamp and discharge devices: systems – Cathode ray tube circuits – Cathode-ray deflections circuits
Patent
1983-06-17
1984-11-20
Blum, Theodore M.
Electric lamp and discharge devices: systems
Cathode ray tube circuits
Cathode-ray deflections circuits
315367, H01J 2970, H01J 2972
Patent
active
044841108
ABSTRACT:
The horizontal-deflection pulses (HA) and the vertical synchronizing pulses (VS) are applied to the count input (Ez) and the reset input (Er) of an upcounter (VZ) whose count outputs are connected to the address inputs (Ea) of a programmable read-only memory (PROM1) via a decoder (DC). The S-shaped characteristic of the deflection-stage current is approximated by portions of constant slope whose associated slope values are stored in the programmable read-only memory (PROM1) under one address each. The pulses of a clock generator (TG2) whose frequency is chosen so that when a first presettable down-counter (RZ1) is set to the highest slope value, its zero state is reached within line period are applied via one of the input-output paths of an AND gate (UG1) to this first presettable down-counter (RZ1), which is preset by the programmable read-only memory (PROM1) via first input-output paths of a multiple AND gate (MU1) and whose zero-state output (AO) is connected to the other input of the AND gate (UG1), while the other inputs of the multiple AND gate (MU1) are fed with the horizontal-deflection pulses (HA). The output pulses of the AND gate (UG1) are divided by a frequency divider (FT) and then counted in synchronism with the field frequency by a first presettable up-counter (VV1) which is preset by a second programmable read-only memory (PROM2) in which a digital word corresponding to the deflection current at the top or bottom of the image is stored. The pulses of another clock generator (TG1) are counted by a second presettable down-counter (RZ2) and a second presettable down-counter (VV2) after passing through one of the input-output paths of a second AND gate (UG2) and a third AND gate (UG3), respectively. The counts of the first presettable up-counter (VV1) preset the second presettable down-counter (RZ2) and the second presettable up-counter (VV2) via the first input-output paths of a second multiple AND gate (MU2) and a third multiple AND gate (MU3), respectively. The horizontal-deflection pulses (HA) are applied to the second inputs of the second and third multiple AND gates (MU2, MU3), whose third inputs are connected, via an inverter (IV) and directly, respectively, to the output (Am) of the first presettable up-counter (VV1) for the most significant bit. The count outputs of the second presettable down- and up-counters (RZ2, VV2) are respectively connected via first and second multiple OR gates (MO1, MO2) to the drive-signal outputs (A', A") for one and the other half of the image, which outputs are also coupled to the other inputs of the second AND gate (UG2) and the third AND gate (UG3), respectively.
REFERENCES:
patent: 4171504 (1979-10-01), Strathman
patent: 4251754 (1981-02-01), Navarro et al.
Blum Theodore M.
IT&T Industries, Inc.
Lenkszus Donald J.
LandOfFree
Monolithic integrated vertical-deflection circuit for television does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Monolithic integrated vertical-deflection circuit for television, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Monolithic integrated vertical-deflection circuit for television will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2191006