Monolithic discrete-time digital convolution circuit

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364758, 364754, 364768, G06F 738

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active

044893930

ABSTRACT:
A monolithic convolver circuit making extensive use of "pipelined" architecture to ensure high speed by concurrency of processing, and having a repetitive stage to facilitate chip layout and manufacture. The circuit includes a multiplier and an adder in each stage. The adders produce a sequence of summation terms concurrently and include shift registers to move and accumulate the results of convolution. The adders produce only partial sums at each stage, to increase processing speed. Full computation of carries is deferred until the very end, and performed in a separate conditional sum adder.

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Steven K. Kawahara et al., "A One-Micron Bipolar VLSI Convolver," 1981 IEEE International Solid-State Circuits Conf., Digest of Tech. Papers, pp. 226-227.

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