Monolithic digital phaselock loop circuit having an expanded pul

Details Monolithic digital phaselock loop circuit having an expanded pul Monolithic digital phaselock loop circuit having an expanded pul

1991-10-30

1992-12-01

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 11, 331 14, 331 17, 331 25, H03L 7087, H03L 718

Patent

active

051682451

ABSTRACT:
A monolithic phaselock loop circuit (PLL) for controlling the phase and frequency of a VCO to compensate for process induced variations in the VCO natural frequency and to extend the pull-in range by .+-.50% of the frequency of a reference clock. The PLL is comprised of a VCO, a digital phase comparator, a digital frequency divider and a digital sequential phase error detector (SPED). The SPED circuit comprises two up-down counters, one to control the phase; the other, the frequency; a first one-shot circuit that drives the phase up-down counter to detect every level transition of the reference clock and a second one-shot circuit that drives the frequency up-down counter to provide a pulse for every falling edge of the reference clock; and a shift register responsive to the phase comparator to store the value of the phase comparator thereby providing indication of a frequency lock between the reference clock and the VCO.

REFERENCES:
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patent: 4908582 (1990-03-01), Kawano et al.
patent: 4920322 (1990-04-01), Ruijs
patent: 4929916 (1990-05-01), Fukuda
patent: 4942370 (1990-07-01), Shingemori

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