Static information storage and retrieval – Floating gate
Reexamination Certificate
2006-06-20
2006-06-20
Zarabian, Amir (Department: 2827)
Static information storage and retrieval
Floating gate
C365S185050, C365S185110, C365S185280, C257S340000, C257S797000
Reexamination Certificate
active
07064978
ABSTRACT:
A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a tunneling insulation layer, the floating gate is aligned with edges of the source region and the drain region and having a width defined by a width of the edges of the source the drain. The floating gate and control gate have a relatively small coupling ratio of less than 50% to allow scaling of the nonvolatile memory cells. The nonvolatile memory cells are programmed with channel hot electron programming and erased with Fowler Nordheim tunneling at relatively high voltages.
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Hsu Fu-Chang
Lee Peter W.
Ma Han-Rei
Tsao Hsing-Ya
Ackerman Stephen B.
Aplus Flash Technology Inc.
Knowles Billy
Pham Ly Duy
Saile George D.
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