Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1997-04-09
2000-06-13
Le, Dieu-Minh T.
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
714 22, 714 55, 714734, G06F 1100
Patent
active
060761725
ABSTRACT:
Accompanied by turning on power, power ON reset pulse from a power ON reset generation circuit is input to CPU and a fail determining circuit. After receiving the power ON reset pulse, the fail determining circuit intentionally outputs a fail detection signal. The CPU intentionally stops output of PRUN signal after confirming that fail detection signal. WDT confirms that output of the PRUN signal from the CPU is stopped in a predetermined time interval T and outputs PRUN abnormality signal. A reset pulse generation circuit confirms that PRUN abnormality signal is supplied from the WDT and outputs a reset pulse. A fail determining circuit receives a reset pulse and stops output of fail detection signal. When the fail determining circuit stops output of the fail detection signal, the CPU determines that the WDT, the reset pulse generation circuit and the fail determining circuit are in normal state. Thus, this monitoring system for electronic control unit is capable of diagnosing the WDT, the reset pulse generation circuit and the fail determining circuit at the time of self-diagnosis.
REFERENCES:
patent: 4670676 (1987-06-01), Nishitani
patent: 5113504 (1992-05-01), Matsuda
patent: 5247163 (1993-09-01), Ohno et al.
patent: 5408648 (1995-04-01), Gokan et al.
patent: 5576650 (1996-11-01), Hirotani et al.
Ino Junsuke
Kimura Takashi
Le Dieu-Minh T.
Nissan Motor Co,. Ltd.
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