Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Encapsulating
Reexamination Certificate
1998-08-12
2001-07-10
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Encapsulating
C438S106000, C438S121000, C438S124000, C438S125000, C438S126000
Reexamination Certificate
active
06258632
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a molded semiconductor device and a process for the production thereof, wherein the molded semiconductor device uses bonding wires, that are directly connected to external electrodes on the surface of the semiconductor elements, as external terminals for connection to external circuitry.
BACKGROUND OF THE INVENTION
Molded semiconductor devices are created by means of steps such as: a dicing step in which individual semiconductor elements (semiconductor chips) formed on a wafer are separated out; a die bonding step in which the separated individual semiconductor chip is loaded onto a lead frame; a wire bonding step in which electrical connection is made between electrode pads on the semiconductor chip and the inner leads of the lead frames using fine wire such as gold wire, aluminium wire, etc.; and a packaging step in which the semiconductor chip, the fine wires attached to the semiconductor chip and the inner leads are sealed in resin. Generally the method used for sealing the semiconductor chip in resin is the pressure molding method, the potting method, the transfer molding method, or the like.
FIG. 1
shows a prior art molded semiconductor device which is a small outline package (SOP) device. The semiconductor chip (
1
) is anchored by means of a conducting adhesive to the lead frame's (
2
) die pad part (
3
), which carries the semiconductor element. The lead frame (
2
) is equipped with an inner lead part (
6
) within the molded resin unit and an outer lead part (
9
) outside of the molded resin unit (molding compound). The semiconductor chip (
1
), the die pad part (
3
), the inner lead part (
6
), etc., are encased and protected by the molded resin unit (
8
).
The molded resin unit (
8
) comprises, for example, epoxy resin, etc., and is formed by a method such as the transfer molding method. In addition, the outer lead part (
9
) is formed so that connection between the tips and external circuitry can be easily achieved. The inner lead part (
6
) is arranged so that within the molded resin unit (
8
) the tips thereof face towards the semiconductor chip (
1
). Also, the bonding tip parts of the inner lead part (
6
) are connected to external electrodes (
5
) (for example, electrode pads) formed on the main surface of the semiconductor chip, by means of bonding wires (
7
) made of gold, aluminium, or the like. On the main surface of the semiconductor chip (
1
) the external electrodes (
5
) are surrounded by an insulating layer (
15
) comprising SiO
2
or the like.
Next, a prior art molding process which involves the loading of chips onto lead frames will be explained with reference to
FIGS. 2 and 3
.
FIG. 2
shows a plan of a lead frame loaded into a die,
FIG. 3
shows a cross section of a lead frame positioned in the cavity of a die, and comprises a cross section corresponding to the line A-A′ in FIG.
2
. The lead frame (
2
) is formed by etching or cutting raw material such as copper, iron—42 wt.% nickel alloy, or the like, in sheet or coil form. Etching is carried out in accordance with a resist pattern formed on the raw material, and the inner lead tips are completed by surface processing involving plating with gold or silver. Similarly, with the cutting method, the raw material is patterned to form the shape of the lead frame using a cutting die.
The lead frame (
2
) comprises an outer frame (
10
), a die pad (
3
) onto which the semiconductor chips (
1
) are loaded, inner leads (
6
) which are sealed in tho molded resin unit, and outer leads (
9
) which lead out from the molded resin unit, and is a long body formed by repeating these parts as single units. Semiconductor chip (
1
) is bonded to the die pad (
3
), and the semiconductor chip (
1
) electrode pads (external electrodes, not shown) are connected to the inner leads (
6
) by means of bonding wires (
7
). With the lead frame (
2
) set up in the transfer molding die (
12
), the lead frame's (
2
) inner leads (
6
), die pad (
3
) and die pad (
3
) support pins (
11
) are accommodated within the cavity (
16
) formed by the depressions in the top die (
13
) and the bottom die (
14
) (the extent of this cavity is shown by the dotted line in FIG.
2
. This cavity (
16
) is filled with the resin that forms the molded resin unit. The entrance gate (
17
) through which the resin is injected into this cavity (
16
) is formed in the shorter side of the rectangular cavity (
16
). This gate is located along the line A-A′ in FIG.
2
. The semiconductor device's resin sealed package changes very little in contrast to the tendency of the semiconductor chip to become highly dense and expand. Accordingly the proportion occupied by the semiconductor chip within the molded resin unit increases, and in particular with semiconductor devices that use thin packaging, it is difficult to seal the resin uniformly.
In addition, as stated above, with prior art molded semiconductor devices, semiconductor chips are sealed in resin using a lead frame. However, with the package of
FIG. 1
, because of the use of lead frames and substrates, a lead frame or substrate must be manufactured for each product, and a considerable amount of time must be set aside for the design and production of these. Also, the reality is that because the thickness of the lead frame or substrate is quite considerable compared to the thickness of the total package, it is difficult to produce ultra-thin packages.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a molded semiconductor device that makes it possible to achieve ultra-thin packages rapidly and at low cost.
To achieve the above object, the present invention provides a molded semiconductor device which comprises a semiconductor chip, a plurality of bonding wires wherein one end of each bonding wire is coupled to the semiconductor chip, and a molding compound encasing the semiconductor chip and the bonding wires, wherein another end of each bonding wire is exposed directly to a surface of the molding compound.
Other objects, features, and advantages of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
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patent: 4530152 (1985-07-01), Roche et al.
patent: 5200362 (1993-04-01), Lin et al.
patent: 5565709 (1996-10-01), Fukushima et al.
patent: 6001671 (1999-12-01), Fjelstad
patent: 6081978 (2000-07-01), Utsumi et al.
patent: 63-249345 (1988-10-01), None
patent: 64-82656 (1989-03-01), None
patent: 1-106456 (1989-04-01), None
patent: 3-4543 (1991-01-01), None
patent: 3-24752 (1991-02-01), None
patent: 3-297163 (1991-12-01), None
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Niebling John F.
Zarneke David
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