Molded dielectric layer in print-patterned electronic circuits

Details Molded dielectric layer in print-patterned electronic circuits Molded dielectric layer in print-patterned electronic circuits

2006-12-22

2009-08-18

Tsai, H. Jey (Department: 2895)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S780000, C438S781000, C257SE23134

Reexamination Certificate

active

07576000

ABSTRACT:
A method forms a first active electronic layer, prints an array of pillars on the first active electronic layer, dispenses a curable polymer over the array of pillars, molds the curable polymer by contacting the curable polymer with a mold structure to displace the curable polymer from upper surfaces of the pillars, cures the curable polymer to produce a hardened polymer, and removes the array of pillars to leave an array of holes in the hardened polymer. Another method provides a substrate having selected areas, prints an array of pillars on the substrate, dispenses a curable polymer over the array of pillars, molds the curable polymer by contacting the array of pillars with a mold structure to displace the curable polymer from upper surfaces of the pillars, cures the curable polymer to produce a hardened polymer, and removes the array of pillars to leave an array of holes in the hardened polymer corresponding to the selected areas. Another method forms a first active electronic layer on a substrate, prints an array of conductive pillars on the active electronic layer on a substrate, dispenses a curable polymer on the array of conductive pillars, molds the curable polymer by contacting the array of pillars with a mold structure to displace the curable polymer from the upper surfaces of the conductive pillars, curing the curable polymer to produce a hardened polymer, and forms a second active electronic layer on the hardened polymer such that the second active electronic layer is in electrical connection with the first active electronic layer through the conductive pillars.

REFERENCES:
patent: 2005/0133788 (2005-06-01), Chabinyc et al.
patent: 2005/0142855 (2005-06-01), Choi

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