Mold design and semiconductor package

Details Mold design and semiconductor package Mold design and semiconductor package

2008-05-23

2011-10-04

Sandvik, Benjamin (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With provision for cooling the housing or its contents

C257SE23101, C257SE21505, C438S122000

Reexamination Certificate

active

08030761

ABSTRACT:
A chip package includes a carrier having a first and a second major surface. The first major surface includes an active region surrounded by an inactive region. The chip package includes contact pads in the active region for mating with chip contacts of a chip. A support structure is disposed on the inactive region of the first major surface. The support structure forms a dam that surrounds the active region. When a chip or chip stack is mounted in the active region, spacing exists between the dam and the chip or chip stack. The spacing creates convention paths for heat dissipation.

REFERENCES:
patent: 6060340 (2000-05-01), Chou
patent: 6157080 (2000-12-01), Tamaki et al.
patent: 6316291 (2001-11-01), Weber
patent: 7247509 (2007-07-01), Yamauchi et al.
patent: 7598617 (2009-10-01), Lee et al.
patent: 2005/0121757 (2005-06-01), Gealer

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