Moisture repellant integrated circuit dielectric material combin

Details Moisture repellant integrated circuit dielectric material combin Moisture repellant integrated circuit dielectric material combin

1999-05-06

2000-02-22

Chaudhari, Chandra

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

438760, 438761, 438788, H01L 2144

Patent

active

060280131

ABSTRACT:
A method of making an inter-metal oxide layer over a patterned metallization layer of a substrate, and the resulting structure having the inter-metal oxide layer are provided. The method includes depositing a fluorine doped high density plasma (HDP) oxide layer over the patterned metallization layer. The fluorine doped HDP oxide layer is configured to evenly deposit in high aspect ratio regions of the patterned metallization layer. The method also includes depositing a plasma enhanced chemical vapor deposition (PECVD) oxide layer over the fluorine doped HDP oxide layer. The PECVD oxide layer is doped with a phosphorous material. A CMP operation is then performed over the PECVD oxide layer to remove topographical oxide variations, such that the CMP operation will be configured to preferably leave at least a coating of the PECVD oxide layer over the HDP oxide layer. In this example, the phosphorous material in the PECVD oxide is configured to assist in creating a substantial moisture barrier over the fluorine doped HDP oxide layer and thus protect metallization lines from corrosion. In an alternative example, a non-conductive, highly moisture resistant barrier layer can be deposited in between the fluorine doped HDP oxide layer and the PECVD oxide.

REFERENCES:
patent: 5494854 (1996-02-01), Jain
patent: 5763010 (1998-06-01), Guo et al.
patent: 5943261 (1998-08-01), Lee

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