Modulo address generator with precomputed comparison and correct

Details Modulo address generator with precomputed comparison and correct Modulo address generator with precomputed comparison and correct

1997-08-27

2000-04-11

Nguyen, Hiep T

Electrical computers and digital processing systems: memory

Address formation

Generating a particular pattern/sequence of addresses

711218, 711219, 711220, G06F 1206

Patent

active

060498587

ABSTRACT:
In accordance with the present invention, an address arithmetic unit provides a modulo addressing technique for addressing memory locations in a circular buffer. The address arithmetic unit includes a sign detector adapted to determine whether a sum of an address pointer and a precomputed comparison term is of a first state or a second state. A first adder adds an address pointer and a precomputed correction term to generate a first potential next address pointer. A second adder, operating in parallel with the first adder, adds the address pointer and a displacement to generate a second potential next address pointer. A selector adapted to select the first potential next address pointer as an output when the sign detector output and a sign bit of the displacement are different, and to select the second potential next address pointer as an output when the sign detector output and a sign bit of the displacement are the same.

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