Electrical computers and digital processing systems: memory – Address formation – Generating a particular pattern/sequence of addresses
Patent
1997-09-18
2000-06-06
Thai, Tuan V.
Electrical computers and digital processing systems: memory
Address formation
Generating a particular pattern/sequence of addresses
711219, 711211, 711200, G06F 1200
Patent
active
060732288
ABSTRACT:
A modulo address generation circuit for generating multiple-word memory accesses for use in a computer system. The circuit includes an address pointer latch for retaining a current address pointer, an adder for receiving the current address pointer as a first input and a displacement as a second input. The adder for adding the inputs to provide an output. A comparator compares the current address pointer to an ending address of a circular buffer ignoring least significant bits thereof when the displacement is greater than one. The comparator provides an output that is a first state when the inputs are the same and an output that is a second state when the outputs are different. A control circuit is adapted to receive an indicator of the beginning address of the circular buffer, an indicator of the current address pointer, and an indicator of the ending address of the circular buffer. The control circuit provides the output of the adder to the address pointer latch as an updated address pointer when the indicators take on predetermined values and the comparator output is in the second state. The control circuit provides the beginning address to the address pointer latch as an updated address pointer when the indicators take on predetermined values and the comparator output is in the first state. An advanced address pointer may be used to enhance performance in misaligned memory accesses.
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Holmqvist Carl R.
Rhodes Douglas J.
Tate Larry R.
Thierbach Mark Ernest
Lucent Technologies - Inc.
Smith David L.
Thai Tuan V.
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