Modulo address generating circuit and method with reduced area a

Details Modulo address generating circuit and method with reduced area a Modulo address generating circuit and method with reduced area a

1997-08-05

1999-05-18

Mai, Tan V.

Boots, shoes, and leggings

364769, G06F7/38;7/50

Patent

active

059056657

ABSTRACT:
A modulo address generating apparatus and method are disclosed which obtain high speed performance with reduced integrated circuit area. A modulo address generator according to the present invention includes a first adder for adding a current address to an address increment to generate an incremented address, an inverter for producing a complement of a maximum address, a second adder for generating a circular correction value by adding the complement of the maximum address to a minimum address, an adder/subtracter for generating a corrected next address by adding or subtracting the circular correction value to or from the incremented address according to a sign value of the address increment, a comparator for checking whether the incremented address is within an address range defined by the maximum and minimum addresses, and a multiplexor controlled by the comparator which selects the incremented address for output as a next address when the incremented address is within the address range and selects the corrected address for output as the next address when the incremented address is outside the address range.

REFERENCES:
patent: 4800524 (1989-01-01), Roesgen
patent: 4833602 (1989-05-01), Levy et al.
patent: 5249148 (1993-09-01), Catherwood et al.
patent: 5276827 (1994-01-01), Delaruelle et al.
patent: 5511017 (1996-04-01), Cohen et al.
patent: 5659700 (1997-08-01), Chen et al.

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