Electrical computers and digital data processing systems: input/ – Input/output data processing – Transfer direction selection
Reexamination Certificate
1999-08-17
2002-10-29
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Transfer direction selection
C710S033000, C710S300000
Reexamination Certificate
active
06473813
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to the field of digital data systems and associated bus arrangements and, more particularly, to a highly advantageous address translation arrangement for use in a digital system.
Digital systems incorporating a plurality of modules have been configured in a number of ways with regard to the manner in which data is transferred between the modules using a bus arrangement that interconnects the modules. Certain modules such as, for example, memory management modules may serve to select one of a number of memory modules to serve as a destination module that ultimately receives a data transfer originating from a source module. In accordance with one prior art implementation (not shown), a common bus interconnects the source module, the memory management module and the destination module. A data transfer is performed by first transferring the data from the source module to the memory manager module. Thereafter, the data is transferred from the memory manager module to the destination module. It should be appreciated that, while the bus arrangement in this implementation is flexible in nature (i.e., additional modules may be connected to the common bus), the memory manager module must disadvantageously be configured with sufficient memory to store the entirety of the data transfer. A further disadvantage in this implementation resides in the fact that the data transfer is, in essence, performed twice. Accordingly, for a single data transfer, twice the bandwidth associated with performing the data transfer a single time is required.
Attention is now directed to
FIG. 1
which illustrates another prior art implementation for performing a data transfer using a system that is generally indicated by the reference number
10
. System
10
includes modules A-D which are interconnected by a bus arrangement
12
. The bus arrangement includes buses
12
a-c
which define dedicated data transfer paths between the modules, as illustrated. When compared with the previously described implementation, it should be appreciated that bus arrangement
12
is configured in a customized manner to establish required data transfer paths in hardware. That is, a single bus does not interconnect all of the modules. Rather, provisions for data paths are made in hardware (buses
12
a-c
) after the need for a particular data path becomes evident.
Still referring to
FIG. 1
, for purposes of the present discussion, a data transfer is contemplated in which module A serves as a source module while either module C or D may serve as the destination module. In order to reach the destination module, however, bus arrangement
12
is configured such that the data transfer must pass through module B. This implementation is advantageous over the previously discussed implementation for the reason that module B is not required to store a complete data transfer. Unfortunately, however, this implementation is disadvantageous for the reason that the bus arrangement is highly inflexible. If additional modules such as, for example, modules E and F (shown in phantom) are added, dedicated buses
12
d
and
12
e
(also shown in phantom) must also typically be added. Thus, data may be transferred between module E and module A on bus
12
d
and between module F and module C on bus
12
e
. Moreover, it is likely that the customized bus arrangement interconnecting modules A-C comprising buses
12
a-c
will not facilitate data transfers between modules E and F via modules A-C. For this purpose, still another bus
12
f
will be added in hardware. It is apparent that some point may be reached at which the system will be unable to accommodate further expansion due to architectural constraints so as to require redesign.
The present invention introduces a highly advantageous address translation arrangement which resolves the foregoing disadvantageous and which provides still further advantages, as will be described.
SUMMARY OF THE INVENTION
As will be described in more detail hereinafter, there is disclosed herein an address translation arrangement and associated method for use in a digital system. Like the system of
FIG. 1
, a system manufactured in accordance with the present invention includes a plurality of modules and a bus arrangement which interconnects the modules for executing data transactions using the bus arrangement. Each data transaction includes an address portion which defines a data portion. In accordance with the present invention, however, the improvement comprises a first one of the modules configured for initiating the address portion of the data transaction on the bus arrangement. A second one of the modules is configured for receiving the address portion of the transaction on the bus arrangement from the first module and includes a translation arrangement configured for selecting, based on a set of criteria including the address portion, (i) the second module to participate in the data portion with the first module or, (ii) as an alternative, generating a translated address portion such that the translated address portion identifies one of the modules, other than the first or second module and, thereafter, sends the translated address portion to the identified one of the modules such that the identified module then participates in the data portion of the transaction with the first module.
REFERENCES:
patent: 4263649 (1981-04-01), Lapp, Jr. et al.
patent: 4814974 (1989-03-01), Narayanan et al.
patent: 4847757 (1989-07-01), Smith
patent: 5634060 (1997-05-01), Jennings
patent: 6119188 (2000-09-01), Sheafor et al.
Gaffin Jeffrey
Kim Harold
Pritzkau Michael
Sitera, Inc.
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