Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2000-02-15
2001-10-09
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S108000, C438S110000, C438S459000, C438S464000, C257S528000, C257S532000, C257S684000, C257S700000
Reexamination Certificate
active
06300161
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the packaging of semiconductor devices, and more particularly to module and method for interconnecting integrated circuits (ICs) on a semiconductor substrate.
BACKGROUND OF THE INVENTION
As the operational frequency and integration increases, the overall performance of electronic systems becomes increasingly sensitive to the capacitive, inductive and resistive characteristics of the ICs associated therewith, as well as the structures employed to interconnect the ICs. The aforementioned characteristics result in unwanted currents propagating along either a DC power trace or a signal trace that degrade the operation of the ICs. For example, during operation, the amount of current demand of an IC, such as a processor, can vary rapidly between milliamps to tens of amps. This may produce voltage spike in the power plane through which current is supplied to the IC. The magnitude of spikes are proportional to the frequency of operation of the IC. This produces a voltage drop across the inductance associated with the power planes in direct proportion to the rate of change of current. The voltage drop may substantially reduce the operational frequency of the IC. Prior art techniques to solve this problem include use of off-chip de-coupling capacitors distributed throughout the power plane on the printed circuit board to which the integrated circuit is mounted. However, the frequency of operation of the off-chip de-coupling capacitors were limited.
U.S. Pat. No. 5,973,910 to Gardner discloses a de-coupling capacitor that attempts to overcome the problems associated with off-chip de-coupling capacitors. Specifically, Gardner discloses reducing noise associated with current propagating along a DC power line embedded in an IC by connecting a de-coupling capacitor as close to a load as possible. To that end, Gardner discloses a de-coupling capacitor incorporated into an integrated circuit. The capacitor is disposed over a first region of a substrate comprising electronic circuitry, and not over a second region of the substrate. The capacitor comprises a lower and an upper conductive layer separated by an interposing insulative layer. An additional insulative layer is disposed beneath the lower conductive layer while another insulative layer is disposed above the upper conductive layer.
U.S. Pat. No. 5,872,697 to Christensen et al. discloses an integrated circuit having a de-coupling capacitor integrally formed therewith. The capacitor includes a dielectric film disposed over a final metal layer of the integrated circuit. A conductive film is disposed over the dielectric layer to provide capacitance in the dielectric layer. In this manner, the performance of the integrated circuit is described as being enhanced. Specifically, the performance is enhanced by facilitating higher switching speeds due to the faster response of the capacitor to power supply bounce resulting from large currents produced by the high speed switching. A drawback with the prior art techniques for reducing surge currents is that they typically require greatly increasing the area required to manufacture an integrated circuit due to the formation of the de-coupling capacitor or necessitate a limit in the operational frequency of the integrated circuit.
What is needed, therefore, is a technique for reducing surge currents without increasing the area required to form the integrated circuit or reducing the operational frequency of the same.
SUMMARY OF THE INVENTION
A module to interconnect ICs includes an insulative body that features a de-coupling capacitor defined by a dielectric layer disposed between conductive traces having differing resistivities. Typically, the de-coupling capacitor provides a capacitance per unit area in the range of 50 nF/cm
2
to 250 nF/cm
2
. With this structure, the de-coupling capacitor provides a much lower impedance over a wider range of frequencies, and at higher frequencies, than previously attainable. In this manner, the surge currents associated with the inductance in the power planes is reduced.
The insulative body has, disposed therein, a conductive bond pad and a plurality of spaced apart conductive traces, one of which is in electrical communication with the bond pad. Each of the plurality of conductive traces is formed from a material having a resistivity associated therewith. The resistivity of the material from which one of the plurality of conductive traces is formed, defining a first conductive trace is greater than the resistivity of the material from which the remaining conductive traces are formed. In another embodiment, one of the remaining conductive traces is disposed adjacent to, but spaced-apart from, the first conductive trace, defining the de-coupling capacitor therebetween.
The method according to the present invention includes providing an insulative substrate and forming a conductive first layer on the substrate having a resistivity associated therewith. Adjacent to the conductive first layer, a first insulative layer is formed, followed by formation of a second conductive layer adjacent to the first insulative layer. The second conductive layer has a resistivity associated therewith that is less than the resistivity associated with the first conductive layer. Formed adjacent to the second conductive layer is a second insulative layer, with a third conductive layer being formed adjacent to the second conductive layer. A fourth conductive layer is formed adjacent to the third insulative layer. A contact point, in electrical communication with the third conductive layer, is formed adjacent to the fourth conductive layer.
These and other embodiments of the present invention, along with many of its advantages and features, are described in more detail in the text below and the attached figures.
REFERENCES:
patent: 5134539 (1992-07-01), Tuckerman et al.
patent: 5135889 (1992-08-01), Allen
patent: 5583739 (1996-12-01), Vu et al.
patent: 5633785 (1997-05-01), Parker et al.
patent: 5729047 (1998-03-01), Ma
patent: 5872697 (1999-02-01), Christensen et al.
patent: 5874770 (1999-02-01), Saia et al.
patent: 5973910 (1999-10-01), Gardner
patent: 6075711 (2000-06-01), Brown et al.
patent: WO 98/18303 (1998-04-01), None
“Processors Put Pressure on Packages, A Review of the Packages Housing Modern PC Processors”, Dennis Herrell; Microprocessor Report; Dec. 27, 1999; pp. 12-15.
Goetz Martin P.
Zasio John
Alpine Microsystems, Inc.
Anya Igwe U.
Brooks Kenneth C.
Smith Matthew
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