Modular partial reconfiguration

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C716S030000, C716S030000, C716S030000, C716S030000, C713S001000, C713S100000, C703S022000

Reexamination Certificate

active

07640526

ABSTRACT:
A method for instantiating a design in programmable logic of an integrated circuit is described. First configuration information is generated for configuration of the static portion of the design. The first configuration information includes routing information for routing static routes of the static portion of the design using interconnect lines. Second configuration information is generated for configuration of the at least one dynamic portion of the design. The first configuration information and the second configuration information are merged to provide third configuration information, the third configuration information being for configuration of the at least one module in the programmable logic.

REFERENCES:
patent: 6260182 (2001-07-01), Mohan et al.
patent: 6292925 (2001-09-01), Dellinger et al.
patent: 6457164 (2002-09-01), Hwang et al.
patent: 6480954 (2002-11-01), Trimberger et al.
patent: 6625794 (2003-09-01), Trimberger
patent: 6665766 (2003-12-01), Guccione et al.
patent: 6678646 (2004-01-01), McConnell et al.
patent: 6903574 (2005-06-01), Chen et al.
patent: 6920627 (2005-07-01), Blodget et al.
patent: 7269724 (2007-09-01), Trimberger et al.
patent: 7301822 (2007-11-01), Walstrum et al.
Rudack et al.; “Self-configuration of a large area integrated multiprocessor system for video applications”; Oct. 25-27, 2000; Defect and Fault Tolerance in VLSI Systems, 2000. Proceedings. IEEE International Symposium on; pp. 78-86.
Sekar et al.; “Configurable platforms with dynamic platform management: an efficient alternative to application-specific system-on-chips”; 2004; VLSI Design, Proceedings. 17th International Conference on; pp. 307-315.
Xilinx, Inc.; U.S. Appl. No. 11/126,130 by Becker et al. filed May 10, 2005.
Pete Sedcole et al.; “Modular Partial Reconfiguration in Virtex FPGAS”; Aug. 24-26, 2005; International Conference on Field Programmable Logic and Applications; pp. 211-216.
Pete Sedcole et al.; “Modular Dynamic Reconfiguration in Virtex FPGAS”; May 2, 2006; Computer and Digital Techniques; IEE Proceedings, vol. 153,Issue 3; pp. 157-164.
U.S. Appl. No. 11/126,130, Becker et al., filed May 10, 2005.
Xilinx, Inc., “The Programmable Logic Data Book,” Apr. 2000, pp. 3-75 to 3-96, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA. 95124.
XAPP290 (v1.0), Lim, Davin et al., “Two Flows for Partial Reconfiguration: Module Based or Small Bit Manipulations”, May 17, 2002, 23 pages, Xilinx, Inc., 2100 Logic Drive, San Jose, CA.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Modular partial reconfiguration does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Modular partial reconfiguration, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Modular partial reconfiguration will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4145250

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.