Modular memory structure having adaptable redundancy circuitry

Details Modular memory structure having adaptable redundancy circuitry Modular memory structure having adaptable redundancy circuitry

2001-11-21

2003-09-09

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S225700, C365S230030

Reexamination Certificate

active

06618301

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a memory structure, and particularly to a modular memory structure having adaptable redundancy circuitry, which uses an enabled line to reduce the fuses required by a programming redundancy circuit and determines the optimized replacement range of defective memory to avoid memory resource waste during the early development phase.
2. Description of the Related Art
In a semiconductor memory device, for example, in a dynamic random access memory (DRAM) or a static random access memory (SRAM) module, redundancy circuitry is widely used.
FIG. 1
is a block diagram of a typical memory block, including redundancy circuitry. As shown in
FIG. 1
, during the verification of each and every cell on the chip before shipping, in the event of data stored into the memory array
16
through the port
12
and the interface
14
encountering defective cells in the memory array
16
, redundancy cells
18
are commonly used to replace defective cells produced by the manufacturing process, thereby increasing the yield. Following the increment of memory density, a hierarchical decoding (not shown) scheme, e.g. top, middle, and bottom addressing, is employed in order to further increase the operating speed and reduce the switching power of decoding operation in DRAM and SRAM. Redundancy replacement is activated where a single row of memory cells or column of memory cells with defects is replaced with a redundancy row or column
18
by making the fuses connect or blow, i.e., programming, to map failure addresses (not shown). However, the number of fuses becomes prohibitively large for this conventional redundancy scheme, particularly in high-density memory, in which a lot of room is consumed by thousands of fuses, so that normal memory cells are compressed into a limited space and the implementation of the circuitry becomes overly complicated.
SUMMARY OF THE INVENTION
Therefore, an object of the invention is to provide a modular memory structure having adaptable redundancy circuitry, which can repair different types of defects to increase the yield of the memory device.
A further object of the invention is to provide a modular memory structure having adaptable redundancy circuitry, which uses an addressing line and an enabled line to reduce the required fuse sets and avoid memory resource waste.
To realize the above and other objects, the invention provides a modular memory structure having adaptable redundancy circuitry, which can repair different types of defects by using an addressing line and an enabled line, thereby increasing the yield of the memory device. The modular memory structure having adaptable redundancy circuitry includes: a plurality of main memory blocks for storing data; a plurality of redundancy memory blocks for replacing the defect memory blocks; a plurality of fuse sets to generate replacement signals by programming the plurality of fuse sets to replace the defect memory positions on the main memory blocks with the corresponding redundancy memory blocks. The replacement signals include an MAT replacement signal, a memory sector replacement signal, and a memory row and column replacement signal. Thus, the optimized replacement range is defined by the signals with the sizes of MAT, sector, and row or column.


REFERENCES:
patent: 5487039 (1996-01-01), Sukegawa
patent: 5991211 (1999-11-01), Kato et al.
patent: 6411556 (2002-06-01), Amano

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