Modular embedded test system for use in integrated circuits

Details Modular embedded test system for use in integrated circuits Modular embedded test system for use in integrated circuits

1999-01-08

2001-02-20

Metjahic, Safet (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S1540PB, C714S724000

Reexamination Certificate

active

06191603

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to integrated circuits, and more particularly, to a circuit design that allows modules embedded in other circuitry to be more easily tested.
BACKGROUND OF THE INVENTION
Large integrated circuits (VSLI) are usually designed from components provided by a library of circuit modules. The design process involves choosing the correct modules and connecting the modules together to provide the desired functionality. A significant fraction of the improvements in the costs and functions of custom integrated circuits is related to the use of well-characterized libraries of standard cells.
In production, there is always a finite error rate. Hence, the integrated circuits must be tested after the fabrication process to assure that the individual chips do not contain fatal fabrication errors. The testing process involves applying a number of test vectors to the integrated circuit. Each test vector specifies the input signals to be applied to the various inputs of the circuit. The tester then examines the outputs generated by the circuit to determine if the circuit is functioning properly. As circuits become more complex, the number of test vectors needed to thoroughly test the circuit becomes increasingly large, and the testing procedure becomes too costly.
If a chip is found to be defective, it may still be repairable if the location of the fault is known. For example, some chip designs include redundant modules that can be connected in a bus to replace a non-functioning module that is currently connected to the bus. Hence, it would be advantageous to be able to test the individual modules to determine which module is responsible for the fault.
Broadly, it is the object of the present invention to provide an improved integrated circuit design that facilitates testing of the integrated circuit.
It is a further object of the present invention to provide an integrated circuit design that allows individual modules to be tested separately.
These and other objects of the present invention will become apparent to those skilled in the art from the following detailed description of the invention and the accompanying drawings.
SUMMARY OF THE INVENTION
The present invention is an integrated circuit having an embedded testing system. The integrated circuit has a plurality of chip input terminals and a plurality of chip output terminals and operates in a test mode and a normal mode. The integrated circuit includes a plurality of core modules and a test data bus. The test data bus has first and second conductors, the first conductor being accessible from one of the chip input terminals and the second conductor being accessible from one of the chip output conductors. Each core module includes an access register for storing an access word, and a plurality of registers connected together as a first scan-chain having an input terminal for receiving data to be shifted into the registers and an output terminal for reading data shifted out of the registers. Each core module also includes a scan-in enable circuit and a scan-out enable circuit. The scan-in enable circuit connects the input terminal of the first scan-chain to the first conductor of the test data bus in response to a first value for the access word. The scan-out enable circuit connects the output terminal of the first scan-chain to an output terminal associated with the core module. The access registers of the core modules are connected together to form an access scan-chain. The access scan-chain has an input terminal accessible from one of the chip input terminals. One of the core modules has an output terminal connected to the second conductor of the test data bus. Core modules may also include other scan-chains used in the testing hardware. In such modules, the scan-in enable circuit further includes circuitry for selecting one of the scan-chains for connection to the first conductor of the test data bus, the selection is determined by the access word. In addition, the scan-out enable circuit further includes circuitry for selecting one of the scan-chains for connection to the output terminal of the core module, the selection is determined by the access word. In the preferred embodiment of the present invention, the first scan-chain provides data values to the core modules that are provided by circuitry external to the core module in the integrated circuit when the integrated circuit is not operating in the test mode. The core modules may be organized in a hierarchy in which one core module is contained within a second core module.


REFERENCES:
patent: 5642362 (1997-06-01), Savir
patent: 5951702 (1999-09-01), Lim et al.
patent: 6044481 (2000-03-01), Kornachuk et al.

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