Modular data transfer architecture

Details Modular data transfer architecture Modular data transfer architecture

2004-12-06

2010-02-16

Patel, Niketa (Department: 2181)

Electrical computers and digital data processing systems: input/

Input/output data processing

Data transfer specifying

C710S003000, C710S009000, C326S047000, C326S041000

Reexamination Certificate

active

07664891

ABSTRACT:
A system on chip (SoC) integrated circuit includes a plurality of computational blocks. A modular data transfer architecture interconnects the computational blocks for intra-chip communications. The computational blocks include an initiator block and a target block, with the initiator block originating a data communication having a global address associated with the target block. The modular data transfer architecture includes a first peripheral module having an initiator port connected to the initiator block to receive the data communication and a second peripheral module having a target port connected to the target block. A first port mapper within the first peripheral module maps the global address to a first peripheral module target port along a data path towards the second peripheral module. A second port mapper within the second peripheral module maps the global address to the target port connected to the target block. The modular data transfer architecture further includes a plurality of internal modules support intra-chip communications. Each internal module has a plurality of initiator ports connected to target ports of other modules and a plurality of target ports connected to initiator ports of other modules. An internal port mapper for each internal module maps the global address to a certain internal module target port along the data path towards the second peripheral module.

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Liang, “An Architecture and Compiler for Scalable On-Chip Communication” Nov. 7, 2004, IEEE, pp. 711-716.

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