Modular CompactPCI backplane

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation

Reexamination Certificate

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Reexamination Certificate

active

06425027

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to computers and the communication pathways within them. It more particularly relates to the backplane of an industrial computer having several segments that conform to the Compact Peripheral Component Interconnect (CompactPCI) Specification and the apparatus used to connect these segments to form a continuous bus across the entire backplane
BACKGROUND OF THE INVENTION
A pathway that provides data communication between two elements of an electric circuit is known as a bus. Buses are used for both communications within the integrated circuits and between the integrated circuits. An important example of the latter is the communication between the Central Processing Unit (CPU) and peripheral components. One of the earliest standards for this type of bus is the Industrial Standard Association (ISA) bus that was developed by IBM in 1984. This bus is 16 bits wide and worked well for early peripheral components with modest bandwidth requirements. However, as the amount of data from peripheral components began to grow the bus became the ‘bottleneck’ in the system. This problem was reduced with the introduction of wider and faster local bus standards. As the speed (frequency) of the bus is increased the physical length of the communication path must be reduced. One current standard local bus is the Peripheral Component Interconnect (PCI) bus LOCI Local Bus Specification, Revision 2.2, Dec. 18, 1998). The PCI bus standard is well suited for personal computers. Industrial computers are however quite different than personal computers. They often use a rack-based chassis. Peripheral components (boards) are inserted into connectors that are located on the backplane at the back of the chassis. The backplane provides a physical connection for the peripheral boards. It also provides electrical connections including power and busing. There are numerous limitations of the PCI bus Specification that make the bus impractical for industrial computers. These limitations include the physical requirements of the bus (e.g. maximum length of several inches), the limitation of a maximum of four slots for peripheral components. Other limitations of the PCI bus standard include connectors that are not robust enough for industrial applications where components are inserted and removed quite often and connectors that present parasitic capacitance on the bus, which tends to limit the number of slots that can be used. However, it is important to maintain PCI Specification compatibility for the bus in industrial computers to access the vast array of integrated circuits that are manufactured for the personal computer market to the PCI Specification.
The CompactPCI Specification was prepared by the PCI Industrial Computer Manufacturers Group (PICMG™) to provide a standard form factor for industrial computers that employs mechanically robust connectors and has a bus that conforms to the PCI Specification. These and other of the features of the CompactPCI Specification are outlined in PICMG 2.0 R2.20—CompactPCI Specification—Jun. 17, 1997, ©1995, 1996, 1997 PCI Industrial Computers Manufacturers Group.
The CompactPCI Specification defines that the PCI compliant bus has a maximum of eight electrical loads. This implies tat the backplane has a maximum of eight slots. Because a System Slot Board is required for the bus a CompactPCI backplane consists of one System Slot (containing e System Slot Board) and up to seven Peripheral Slots for Peripheral Boards. The System Slot Board is responsible for performing system initialization, providing bus arbitration and clock distribution for all boards on the segment. Physically, the System Slot shall be located on either end of the CompactPCI bus segment.
The restriction of eight physical slots (electrical loads) is restrictive for many industrial computers. There are three common approaches for the provision of more Than eight slots on a backplane.
First, the user can purchase two or more 8-slot backplanes and connect them via a standard interface (e.g. LAN, a fibre optic link, etc.). In this case, each CompactPCI bus segment must have its own System Slot Board and must also house the above interface board. It is apparent to those skilled in the art that this can be expensive in terms of both hardware and software, and wasteful in terms of physical space.
Second, while an individual backplane is limited to a maximum of eight slots two segments can be ‘bridged’ together to increase the total number of slots of the backplane. These backplane segments are contained on a single Printed Circuit Board (PCB). The bridge acts as a System Board on the secondary segment (the segment being bridged to), and as a Peripheral Board on the pi segment (the segment being bridged from). The bridge is the provision of a nearly transparent connection between the two bus segments when data must be transferred between devices on different segments. At all other times, the two segments operate independently. Unfortunately, the physical features of the CompactPCI standard have limited the transparent application of bridges due to the requirement that the bridge be connected to both CompactPCI segments at once.
There are two approaches to bridging backplane segments. The bridge circuitry can be permanently affixed directly to the backplane between groupings of up to eight slots. There is some physical space lost due to the presence of the bridge circuitry producing regions of the backplane that cannot be used for CompactPCI peripheral slots. This approach is not very flexible as a different backplane must be manufactured for each unique number of slots and bridges. Further, if the bridging circuitry fails, it can be difficult and time consuming to replace the backplane thereby causing unacceptable downtime. However, this approach is reasonably well suited to high volume applications where the requirements of the backplane are well defined.
A second approach is to place the bridging circuitry on a dedicated, removable board (bridge module). This bridge module could be of the form where it is inserted in slots on the front side of the backplane. In this case it would consume a front side slot on both the primary and secondary bus segments. This approach is very wasteful in terms of physical space since each bridge occupies two physical slots on the front side of the backplane where peripheral boards could be located.
Alternatively the bridge module could be designed to be inserted on the back side of the backplane. In this case the bridge does not consume slots on the front side of the backplane, which again is a single PCB. A special Bridge Slot could be defined which has connections to both primary and secondary segments. A bridge module installed in this slot could perform all of the required bridging functions. Because, the bridge module occupies a physical slot, eliminating a useful peripheral slot, it must use a different pin out than all other standard slots and it must be keyed so that the bridge boards cannot be installed in Peripheral Slots and vice versa. Finally, the number of signal pins available for connecting the bridge board to the backplane is limited, making some bridging arrangements awkward or impossible. This solution still requires a different backplane for each unique number of slots and bridges.
Therefore, there is a need for a modular backplane that complies with the CompactPCI Specification. A modular backplane is defined as a backplane where all of the segments are physically separate entities. This modular backplane would provide flexibility in the number of Peripheral Slots by having backplane segments on separate PCBs to be added and bridged as required. It would also be desirable for the bridging to have the same flexibility while not consuming space on the front side of the backplane that could otherwise be used for Peripheral Boards. This type of backplane would be well suited to low volume applications or research situations. The art does not provide a system that satisfies These requirements.
SUMMARY OF THE INVEN

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