Modular command structure for memory and memory system

Details Modular command structure for memory and memory system Modular command structure for memory and memory system

2011-03-08

2011-03-08

Thomas, Shane M (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S157000, C711SE12003

Reexamination Certificate

active

07904639

ABSTRACT:
A system including a memory system and a memory controller is connected to a host system. The memory system has at least one memory device storing data. The controller translates the requests from the host system to one or more separatable commands interpretable by the at least one memory device. Each command has a modular structure including an address identifier for one of the at least one memory devices and a command identifier representing an operation to be performed by the one of the at least one memory devices. The at least one memory device and the controller are in a series-connection configuration for communication such that only one memory device is in communication with the controller for input into the memory system. The memory system can include a plurality of memory devices connected to a common bus.

REFERENCES:
patent: 4617566 (1986-10-01), Diamond
patent: 4796231 (1989-01-01), Pinkham
patent: 5132635 (1992-07-01), Kennedy
patent: 5204669 (1993-04-01), Dorfe et al.
patent: 5243703 (1993-09-01), Farmwald et al.
patent: 5249270 (1993-09-01), Stewart et al.
patent: 5319598 (1994-06-01), Aralis et al.
patent: 5404460 (1995-04-01), Thomsen et al.
patent: 5430859 (1995-07-01), Norman et al.
patent: 5437018 (1995-07-01), Kobayashi et al.
patent: 5473563 (1995-12-01), Suh et al.
patent: 5473566 (1995-12-01), Rao
patent: 5473577 (1995-12-01), Miyake et al.
patent: 5535357 (1996-07-01), Moran et al.
patent: 5636342 (1997-06-01), Jeffries
patent: 5721840 (1998-02-01), Soga
patent: 5729683 (1998-03-01), Le et al.
patent: 5740379 (1998-04-01), Hartwig
patent: 5802399 (1998-09-01), Yumoto et al.
patent: 5806070 (1998-09-01), Norman et al.
patent: 5828899 (1998-10-01), Richard et al.
patent: 5859809 (1999-01-01), Kim
patent: 5959930 (1999-09-01), Sakurai
patent: 6002638 (1999-12-01), John
patent: 6091660 (2000-07-01), Sasaki et al.
patent: 6144576 (2000-11-01), Leddige et al.
patent: 6148363 (2000-11-01), Lofgren et al.
patent: 6208556 (2001-03-01), Akaogi et al.
patent: 6230233 (2001-05-01), Lofgren et al.
patent: 6295618 (2001-09-01), Keeth
patent: 6304921 (2001-10-01), Rooke
patent: 6317350 (2001-11-01), Pereira et al.
patent: 6317352 (2001-11-01), Halbert et al.
patent: 6317812 (2001-11-01), Lofgren et al.
patent: 6438064 (2002-08-01), Ooishi
patent: 6442098 (2002-08-01), Kengeri
patent: 6453365 (2002-09-01), Habot
patent: 6456528 (2002-09-01), Chen
patent: 6594183 (2003-07-01), Lofgren et al.
patent: 6601199 (2003-07-01), Fukuda et al.
patent: 6643728 (2003-11-01), Crutchfield et al.
patent: 6658509 (2003-12-01), Bonella et al.
patent: 6680904 (2004-01-01), Kaplan et al.
patent: 6715044 (2004-03-01), Lofgren et al.
patent: 6717847 (2004-04-01), Chen
patent: 6754807 (2004-06-01), Parthasarathy et al.
patent: 6763426 (2004-07-01), James et al.
patent: 6799235 (2004-09-01), Bormann et al.
patent: 6807106 (2004-10-01), Gonzales et al.
patent: 6816933 (2004-11-01), Andreas
patent: 6850443 (2005-02-01), Lofgren et al.
patent: 6853557 (2005-02-01), Haba et al.
patent: 6853573 (2005-02-01), Kim et al.
patent: 6928501 (2005-08-01), Andreas et al.
patent: 6944697 (2005-09-01), Andreas
patent: 6950325 (2005-09-01), Chen
patent: 6978402 (2005-12-01), Hirabayashi
patent: 6996644 (2006-02-01), Schoch et al.
patent: 7031221 (2006-04-01), Mooney et al.
patent: 7032039 (2006-04-01), DeCaro
patent: 7111140 (2006-09-01), Estakhri et al.
patent: 7130958 (2006-10-01), Chou et al.
patent: 2002/0161941 (2002-10-01), Chue et al.
patent: 2002/0188781 (2002-12-01), Schoch et al.
patent: 2003/0009612 (2003-01-01), Latta
patent: 2004/0001380 (2004-01-01), Becca et al.
patent: 2004/0024960 (2004-02-01), King et al.
patent: 2004/0039854 (2004-02-01), Estakhri et al.
patent: 2004/0148482 (2004-07-01), Grundy et al.
patent: 2004/0230738 (2004-11-01), Lim et al.
patent: 2004/0256638 (2004-12-01), Perego et al.
patent: 2005/0120157 (2005-06-01), Chen et al.
patent: 2005/0120163 (2005-06-01), Chou et al.
patent: 2005/0160218 (2005-07-01), See et al.
patent: 2005/0166006 (2005-07-01), Talbot et al.
patent: 2005/0207232 (2005-09-01), Delfs et al.
patent: 2005/0289313 (2005-12-01), Roohparvar
patent: 2006/0031593 (2006-02-01), Sinclair
patent: 2006/0198202 (2006-09-01), Erez
patent: 2007/0076479 (2007-04-01), Kim et al.
patent: 2007/0076502 (2007-04-01), Pyeon et al.
patent: 2007/0083701 (2007-04-01), Kapil
patent: 2007/0101096 (2007-05-01), Gorobets
patent: 2007/0109833 (2007-05-01), Pyeon et al.
patent: 2007/0153576 (2007-07-01), Oh et al.
patent: 2007/0233903 (2007-10-01), Pyeon
patent: 2007/0234071 (2007-10-01), Pyeon
patent: 2007/0288686 (2007-12-01), Arcedera et al.
patent: 2008/0016269 (2008-01-01), Chow et al.
patent: 07800456.1 (2009-07-01), None
patent: WO 2005/069150 (2005-07-01), None
Atmel Corp., “High Speed Small Sectored SPI Flash Memory”, pp. 1-22, 2006.
Spansion, 64 Megabit CMOS 3.0 Volt Flash Memory with 50MHz SPI, Spansion, pp. 1-22 (2006).
King, et al., “Communicating with Daisy Chained MCP42XXX Digital Potentiometers”, Microchip AN747, pp. 1-8, 2001.
Intel Corporation, “Intel® Advanced+ Boot Block Flash Memory (C3)”, May 2005, pp. 1-72.
M-Systems Flash Disk Pioneers Ltd., “DiskOnChip H1 4Gb (512MByte) and 8Gb (1 GByte) High Capacity Flash Disk with NAND and x2 Technology”, Data Sheet, Rev. 0.5 (Preliminary), pp. 1-66, 2005.
Tal, A., “Guidelines for Integrating DiskOnChip in a Host System”, AP-DOC-1004, Rev. 1.0, M-Systems Flash Pioneers Ltd., pp. 1-15, 2004.
Samsung Electronics Co. Ltd, ONENAND4G(KFW4G16Q2M-DEB6), ONENAND2G(KFH2G16Q2M-DEB6), ONENAND1G(KFW1G16Q2M-DEB6) Flash Memory, ONENAND™ Specification Ver. 1.2, pp. 1-125, Dec. 23, 2005.
Kennedy, J., et al., “A 2GB/S Point-to-Point Heterogeneous Voltage Capable DRAM Interface for Capacity-Scalable Memory Subsystems”, ISSCC 2004/Session 1/DRAM/11.8, IEEE International Solid-State Circuits Conference, Feb. 15-19, 2004, vol. 1, pp. 214-523.
Oshima, et al., “High-Speed Memory Architectures for Multimedia Applications”, Circuits & Devices, IEEE 8755-3996/97, pp. 8-13, Jan. 1997.
Diamond, S.L., “SyncLink: High: High-speed DRAM for the Future”, Micro Standards, IEEE Micro, pp. 74-75, Dec. 1996.
Atmel, “8-megabit 2.5-volt Only or 2.7-volt Only DataFlash®,” Technical Specification, Atmel, Rev. 2225H-DFLSH (2004).
Samsung Electronics, “K9XXG08UXM Preliminary Flash Memory,” Technical Specification, Samsung Electronics, May 3, 2005, 43 pages.
Silicon Storage Technology, “16 Mbit SPI Serial Flash,” Preliminary Specification, Silicon Storage Technology Inc., (2005), 28 pages.
Stmicroelectronics, “2MBIT, Low Voltage, Serial Flash Memory with 40 MHZ SPI BUS Interface,” Technical Specification, Stmicroelectronics Group of Companies, Aug. 2005, 40 Pages.
“NAND Flash Applications Design Guide,” Revision 1.0, Toshiba America Electronics Components, Inc., (Apr. 2003).
Spansion Data Sheet, S70GL01GN00 MIRRORBIT Flash 1024 Megabit, 3.0 Volt-Only Page Mode Flash Memory Featuring 110 MM MIRRORBIT Process Technology, Jun. 1, 1995.
“HyperTransport TM I/O Link Specification”, Revision 3.00, Document No. HTC20051222-0046-0008, Hypertransport Technology Consortium, pp. 1-428, Apr. 21, 2006.
Hara, T. et al., “A 146mm2 8Gb NAND Flash Memory with 70nm CMOS Technology”, ISSCC Session 2 Non-Volatile Memory 2.1, IEEE International Solid-State Circuits Conference, Feb. 2005, pp. 44, 45 and 584.
Byeon, D. et al., “An 8Gb Multi-Level NAND Flash Memory with 63nm STI CMOS Process Technology”, ISSCC Session 2 Non-Volatile Memory 2.2, IEEE International Solid-State Circuits Conference, Feb. 2005, pp. 46 and 47.
Tanzawa, T. et al., “Circuit Techniques for a 1.8-V-Only NAND Flash Memory”, IEEE Journal of Solid-State Circuits, vol. 37, No. 1, Jan. 2002, pp. 84-89.
Momodomi, M. et al., “A 4 Mb NAND EEPROM with tight programmed Vt Distribution”, IEEE Journal of Solid-State Circuits, vol. 26, Issue 4, Apr. 1991, p

Affiliated with

Also associated with

Rating

Modular command structure for memory and memory system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Modular command structure for memory and memory system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Modular command structure for memory and memory system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2712881