Modular chip integration techniques

Details Modular chip integration techniques Modular chip integration techniques

2007-10-30

2010-06-22

Ghyka, Alexander G (Department: 2812)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

C438S106000, C438S128000, C257SE21499

Reexamination Certificate

active

07741153

ABSTRACT:
Modular chip integration and operation techniques are provided. In one aspect, a method of integrating chips, chip macros or at least one chip in combination with at least one chip macro is provided. The method comprises the following steps. The chips, chip macros or at least one chip in combination with at least one chip macro are assembled on a single carrier platform. One or more signal inputs and outputs are provided to each of the chips, chip macros or at least one chip in combination with at least one chip macro. One or more power and ground inputs and outputs are provided to each of the chips, chip macros or at least one chip in combination with at least one chip macro. The power and ground inputs and outputs to one or more of the chips, chip macros or at least one chip in combination with at least one chip macro are segmented from the power and ground inputs and outputs to at least one other of the chips, chip macros or at least one chip in combination with at least one chip macro so as to form a plurality of voltage islands.

REFERENCES:
patent: 6268660 (2001-07-01), Dhong et al.
patent: 2002/0112496 (2002-08-01), Bash et al.
patent: 2004/0150095 (2004-08-01), Fraley et al.
patent: 2005/0121768 (2005-06-01), Edelstein et al.
patent: 2006/0050488 (2006-03-01), Goodwin
patent: 2008/0164573 (2008-07-01), Basker et al.
patent: 2008/0179755 (2008-07-01), Andry et al.
R. Dennard et al., “Design of ion-implanted MOSFETs with very small physical dimensions,” IEEE Journal of Solid State Circuits, vol. SC-9, No. 5, pp. 256-268 (Oct. 1974).
J.U. Knickerbocker et al., “Development of Next-Generation System-On-Package (SOP) Technology Based on Silicon Carriers With Fine-Pitch Chip Interconnection,” IBM J. Res. & Dev., vol. 49, No. 4/5, pp. 725-753 (Jul./Sep. 2005).

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