Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2007-09-04
2007-09-04
Mai, Tan V. (Department: 2193)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S628000
Reexamination Certificate
active
10435976
ABSTRACT:
A method and apparatuses for performing binary multiplication on signed and unsigned operands of various lengths is discussed herein. It is a concept that may be split into two parts, the first of which is the multiplication hardware itself, a compact, less than-full sized multiplier employing Booth or other type of recoding methods upon the multiplier to reduce the number of partial products per scan, and implemented in such a manner so that a multiplication operation with large operands may be broken into subgroups of operations that will fit into this mid-sized multiplier whose results, here called modular products, may be knitted back together to form a correct, final product. The second part of the concept is the supporting hardware used to separate the operands into subgroups and input the data and control signals to the multiplier, and the algorithms and apparatuses used to align and combine the modular products properly to obtain the final product. These algorithms used to obtain a result as specified by the operation may be as varied as the supporting hardware with which the multiplier may be used, making this multiplier a very flexible and powerful design.
REFERENCES:
patent: 4390961 (1983-06-01), Negi et al.
patent: 4484300 (1984-11-01), Negi et al.
patent: 4809212 (1989-02-01), New et al.
patent: 5262976 (1993-11-01), Young et al.
patent: 5379245 (1995-01-01), Ueda
patent: 5579253 (1996-11-01), Lee et al.
patent: 5684731 (1997-11-01), Davis
patent: 5764558 (1998-06-01), Pearson et al.
patent: 5898604 (1999-04-01), Winterer
patent: 5920497 (1999-07-01), Rim
patent: 6035318 (2000-03-01), Abdallah et al.
patent: 6233597 (2001-05-01), Tanoue et al.
patent: 6523055 (2003-02-01), Yu et al.
“Packed Decimal Multiply Algorithm”; Inventor: Hoffman, RL Schardt, TL; Pubname: TDB 10-75 pp. 1562-1563; Disclosure No. RO8750134; Oct. 1975.
“High Performance Two Cycle Loop Decimal Multiply Algorithm”; Inventors: Angiulli, JM Chang, DC Hornick, JC Nohilly, WJ Zajac, MW; Pubname: TDB 09-81 pp. 1845-1849; Disclosure No. PO8800209; Sep. 1981.
IBM InfoGate; “Improved Table Assisted Addition and Multiplication Methods”; Inventor: Wingert, JA; Pubname: TDB 02-83 pp. 4742-4743; Disclosure No. CT8800050; Feb. 1983.
Busaba Fadi Y.
Carlough Steven R.
Hutton David S.
Krygowski Christopher A.
Rell, Jr. John G.
Augspurger Lynn
Cantor & Colburn LLP
International Business Machines - Corporation
Mai Tan V.
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