Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2007-05-16
2009-02-10
Mai, Tan V (Department: 2193)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
07490121
ABSTRACT:
A method of implementing binary multiplication in a processing device includes obtaining a multiplicand and a multiplier from a storage device; in the event the multiplier is larger than a selected length, partitioning the multiplier into a plurality of multiplier subgroups; in the event the multiplicand is larger than a selected length, partitioning the multiplicand into a plurality of multiplicand subgroups and at least one of zeroing out of unused bits of the multiplicand subgroup and sign-extending a smaller portion of the multiplicand subgroup; establishing a plurality of multiplicand multiples based on at least one of a selected multiplicand subgroup of the plurality of multiplicand subgroups and the multiplicand; selecting one or more of the multiplicand multiples of the plurality of multiplicand multiples based on the each multiplier subgroup of the plurality of multiplier subgroups; and generating a first modular product based on the selected multiplicand multiples.
REFERENCES:
patent: 4390961 (1983-06-01), Negi
patent: 4484300 (1984-11-01), Negi
patent: 4809212 (1989-02-01), New
patent: 5262976 (1993-11-01), Young
patent: 5379245 (1995-01-01), Ueda
patent: 5579253 (1996-11-01), Lee
patent: 5602766 (1997-02-01), Bauer et al.
patent: 5684731 (1997-11-01), Davis
patent: 5764558 (1998-06-01), Pearson
patent: 5898604 (1999-04-01), Winterer
patent: 5920497 (1999-07-01), Rim
patent: 6035318 (2000-03-01), Abdallah
patent: 6233597 (2001-05-01), Tanoue
patent: 6434584 (2002-08-01), Henderson et al.
patent: 6523055 (2003-02-01), Yu
patent: 6611856 (2003-08-01), Liao et al.
RL Hoffman, TL Schardt, “Packed Decimal Multiply Algorithm”, Pubname: TDB 10-75, 2p; Disclosure No. PO8750134; Rochester, MN, USA.
JM Angiulli, DC Chang, JC Hornick, WJ Nohilly, MW Zajac, “High Performance Two Cycle Loop Decimal Multiply Algorithm”; Pubname: TDB 09-81. 5p; Disclosure No. PO8800209; Poughkeepsie, NY, USA.
IBM Infogate, online'; [retrieved on Mar. 13, 2002]; retrieved from the Internet http://infogate.ibm.com:1215/SESS802085/GETDOC/54/5/2. JA Wingert, “Improved Table Assisted and Multiplication Methods”; Pubname: TBD 02-83. 2P; Disclosure No. CT8800050; Charlotte, NC, USA.
Busaba Fadi Y.
Carlough Steven R.
Hutton David S.
Krygowski Christopher A.
Rell, Jr. John G.
Augspurger Lynn
Cantor & Colburn LLP
International Business Machines - Corporation
Mai Tan V
LandOfFree
Modular binary multiplier for signed and unsigned operands... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Modular binary multiplier for signed and unsigned operands..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Modular binary multiplier for signed and unsigned operands... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4122024