Computer graphics processing and selective visual display system – Computer graphics display memory system – Plural storage devices
Reexamination Certificate
1999-08-05
2002-12-17
Tung, Kee M. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Plural storage devices
C345S531000, C345S534000, C345S539000
Reexamination Certificate
active
06496192
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention is directed to digital memory architecture, and in particular to an Architecture for an image transposition memory which uses synchronous DRAM memory devices.
Image transposition memories are used in many applications in which a video image needs to be filtered in both the horizontal and vertical directions. While this filtering may be performed using a two-dimensional spatial filter, as filter kernel sizes increase this option becomes less and less economical. It is well known that many two-dimensional image filters may be decomposed into separate one-dimensional horizontal and vertical filters. This type of decomposition is especially desirable when the filtering process requires a relatively large kernel size.
When an image is processed using separate one dimensional filters, the image data for the rows of the image are processed sequentially, the image is stored and then the samples in the image columns are processed sequentially. The switch from handling sequential samples in image rows to sequential samples in image columns is achieved using an image transposition memory. In a memory of this type, image data are written into the memory as a sequence of samples following the image rows while the image data is read from the memory as a sequence of samples following the image columns.
FIG. 1
is a block diagram of a prior art image format conversion system. In this system, input data are provided to a one-dimensional horizontal interpolator
110
, which changes the number of samples in the image by resizing the image. In an exemplary format converter, the image is first processed in the horizontal direction and then in the vertical direction. The image data provided by the horizontal interpolator
110
is stored into a transpose memory
112
. The transpose memory
112
stores the image data as consecutive samples in raster scan order (i.e. as horizontal lines of samples). The vertical interpolator
114
then reads the samples from transpose memory
112
in column order (i.e. as consecutive samples taken along each column of the image). The interpolator
114
may, for example, perform the same function as the interpolator
110
, to provide image data which is scaled in the same proportion in both the horizontal and vertical directions. The samples provided by the vertical interpolator
114
, however, are not in raster scan order. Accordingly, these samples are applied to a second transpose memory
116
, which stores the image data as consecutive samples along each column of the image and then provides the image data in raster scan order.
To perform a transpose operation, the entire image from one field or frame of a video signal is written into the transpose memory during one field or frame interval and then read out of the transpose memory during the next field or frame interval. As video signals are continuous, this type of access is typically achieved by configuring two field or frame memories in a Ping-Pong arrangement such that image data may be stored into one memory while it is being read from the other memory.
For real time applications, such as a format converter, it is also desirable for the entire memory to be written into or read from in a single field or frame interval. Typically, these speeds are achieved using static random access memory (SRAM). This type of memory, tends to be much more expensive than the more prevalent synchronous dynamic random access memory (SDRAM). Accordingly, it would desirable to provide a memory architecture in which a transpose memory could be made using SDRAM memory devices.
SUMMARY OF THE INVENTION
The present invention is embodied in a memory architecture for a transpose memory which employs SDRAM memory devices.
According to one aspect of the invention, data in the memory is arranged in rows such that elements in a single row may be accessed without latency. The memory architecture includes at least two memory banks such that memory write operations to one bank may be interleaved with memory write operations to the other bank. Samples of the image along one direction are stored into the memory in groups such that corresponding samples in the orthogonal direction are held in the same memory row. The memory write operations are interleaved such that consecutive write operations access respective memory rows in the alternating memory banks. The number of samples in a group of samples is selected such that the total time for displaying the number of samples in the group is at least equal to the set-up latency for the next memory write operation. Accordingly, consecutive groups of samples may be stored continuously into the memory by alternating the memory banks into which they are stored.
According to another aspect of the invention, data along each column of the image is not read continuously because the column data is stored in multiple rows and each row change in the SDRAM interrupts the continuous flow of data. To compensate for the latency in the read operations, the controller advances the first read operation for a particular image line or image column into the horizontal or vertical blanking interval by a number of clock periods equal to the total set-up latency for the line or column. The system includes a first in first out (FIFO) buffer which receives the image data as it is provided from the memory in response to the memory read requests and provides the image data according to the output timing for the transpose memory.
According to another aspect of the invention, the image data or a pixel includes 20 bits comprising a 10-bit luminance value and a 10-bit chrominance value. Each frame of memory used in the system includes four one-megabit (Mb) by 16-bit SDRAM devices and one four-Mb by four-bit SDRAM device. Each of these devices includes respective first and second memory banks.
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A Memory efficient method for fast transposing run-length encoded images by Misra et al, Proceedings of the 5thinternational conference on document analysis an drecognition. Sep. 20-22, 1999.*
“An efficient implemeentation of affine transformation using one-dimensional FFT's” by Pang et al, 1997 IEEE International Conference on Acoustic, Sppech and Signal Processing, vol. 4, 1997, pp. 2885-2888.*
16 Mb Synchronous DRAM-Die Revision D, IBM Corporation, 1/98, pp. 1-41.
Nasoff David
Shreesha Vasanth
RatnerPrestia
Tung Kee M.
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