Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices
Reexamination Certificate
1998-07-07
2001-08-21
Gaffin, Jeffrey (Department: 2841)
Electricity: electrical systems and devices
Housing or mounting assemblies with diverse electrical...
For electronic systems and devices
C257S686000, C365S051000, C365S063000, C365S230030, C438S109000
Reexamination Certificate
active
06278616
ABSTRACT:
The present invention relates in general to the field of semiconductor integrated circuit assembly and packages and more specifically to substantially flat packages forming a set such that the organization of memory chips is modified, and a method for the fabrication.
BACKGROUND OF THE INVENTION
The trend in semiconductor technology to double the functional complexity of its products every 18 months (Moore's “law”), which is still valid today after having dominated the industry for the last three decades, has several implicit consequences. First, the cost per functional unit should drop with each generation of complexity so that the cost of the product with its doubled functionality would increase only slightly. Second, the higher product complexity should largely be achieved by shrinking the feature sizes of the chip components while holding the package dimensions constant; preferably, even the packages should shrink. Third, the increased functional complexity should be parallelled by an equivalent increase in reliability of the product. And fourth, but not least, the best financial profit rewards were held out for the ones who were ahead in the marketplace in reaching the complexity goal together with offering the most flexible products for application.
For semiconductor memory devices, historically the time span of at least three years has been needed between two generations of memory families. The new generation offers a four times larger memory capacity compared to the preceeding generation. Again, shrinking circuit feature sizes and more complex memory hierarchies have been the prerequisite of the new product generation—at high development cost for chip design and fabrication processes, coupled with very expensive investment in costly new manufacturing equipment.
A number of technical advances have recently been achieved in an effort to obtain an advantage in this competitive marketplace. Within the semiconductor memory product families, one of the most promising concepts for shrinking the package outline and thus consuming less area when the device is mounted onto the circuit board, has been the so-called “board-on-chip” design replacing the traditional metallic leadframe. Patent application Ser. No. 9702348-5 entitled “Board on Chip—Ball Grid Array Chip Size Package” has been filed by Texas Instruments in Singapore on Jul. 2, 1997. This patent application for memory products successfully approaches the problem of reducing the area requirement by replacing the traditional leaded package design with a solder ball concept. In addition, it offers a reduction in the height requirement by replacing the leadframe-on-chip assembly with a thinner and more flexible board-on-chip design. An improvement in device height reduction has recently been submitted to Singapore in a patent application entitled “Thin Chip-Size Integrated Circuit Package and Method of Fabrication” (TI—25689, submitted in December 1997). It describes a modified layout of the electrically conductive strips integral with the electrically insulating board within the device in order to achive a lower loop height of the metal wires in the bonding process.
The newly available board-on-chip memory devices have been exploited for assembling so-called “modules” with two or more devices stacked on top of each other and soldered together by reflowing their solder balls or solder columns. Patent application Ser. No. 9703952-3 entitled “High Density Three Dimensional Board-on-Chip Cube” has been filed by Texas Instruments in Singapore on Nov. 5, 1997, and patent application Ser. No. 9703963-0 entitled “High Density 3-Dimensional Stacked Ball Grid Array Integrated Circuit Module” has been filed by Texas Instruments in Singapore on Nov. 6, 1997. A new modification using thin board-on-chip devices entitled “Thin Board-on-Chip Integrated Circuit Unit” has been submitted by Texas Instruments in Singapore, also in 1997.
While the modules of stacked memory devices achieve more memory bits without shrinking the feature sizes of the chip components, they fail to fully utilize the product complexity due to lack of simultaneous modification of the architectural organization of the module. Consequently, a need has arisen for package designs and methods of device fabrication that provide simple, low-cost processes for memory modules of simultaneously increased memory capacity and architectural organization. At the same time, the goals of small product outline and low height limitation should undergo further refinements. Preferably, these improvements should be accomplished using the installed equipment base so that no investment in new manufacturing machines is needed.
SUMMARY OF THE INVENTION
The present invention comprises a high density memory module and a method for fabricating the enabling parts of small outline memory packages whereby the capacity and the organization of the assembled module is multiplied. The present invention also defines the design rules for the pattern of electrically conductive strips integral to the electrically insulating carriers as constituent parts of the memory device packages.
The present invention applies certain rules taken from mathematical group theory of logic arrangement. When two semiconductor devices, each of which have electrical inputs/outputs, are to be combined into a module so that the inputs/outputs of the module acquires an exlusive combination of the inputsloutputs of the two constituent devices, the rule of “exclusive OR” is employed. The invention accomplishes the modification of the architectural organization of the module by designing the electrical routing inside the device packages so that their electrical inputs/outputs are not shared.
It is an object of the present invention to leapfrog to the memory capacity and organization of the next generation of products without redesigning the semiconductor circuit chips.
Another object of the present invention is to provide a design method of electrical connections, as well as a low-cost process for fabrication, for parts of small outline memory packages suitable for producing stacked memory modules.
Another object of the present invention is to introduce package design concepts for semiconductor memory devices which are flexible, so that they can be applied to several families of memory products, and are general, so that they can be applied to several future generations of products.
Another object of the present invention is to provide a low-cost method and system for assembling chip-size packaged devices into thin overall-profile modules.
Another object of the present invention is to provide reliability assurance for the finished product through in-process control at no extra cost.
Another object of the present invention is to minimize the cost of capital investment and to use the installed fabrication equipment base.
These objects have been achieved by the package design of the invention and a mass production process. Various modifications have been employed for the outline of the package parts and the assembly of packages and modules.
In one embodiment of the invention, the selection rules for the electrically conductive patterns integral to the electrically insulating carriers of 64 Mbit DRAM packages are described, for chips in by-4 organization. When two complimentary devices are combined in accordance with the invention, a 128 Mbit memory module in by-8 organization is created.
In another embodiment of the invention, the selection rules for the electrically conductive patterns integral to the electrically insulating carriers of 64 Mbit DRAM packages are described, for chips in by-4 organization. When four complimentary devices are combinded in accordance with the invention, a 256 Mbit memory module in by-16 organization is created.
In other embodiments of the invention, modules of eight devices in by-4 organization are combinded according to the invention to create eight-times the memory capacity in by-32 organization.
Other embodiments of the invention illustrate the stacking of low profile, high density modules.
The te
Gelsomini Tito
Swee Yong Khim
Yew Chee Kiang
Gaffin Jeffrey
Honeycutt Gary C.
Navarro Arthur I.
Telecky Fred
Texas Instruments Incorporated
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