Modifying a design layer of an integrated circuit using...

Details Modifying a design layer of an integrated circuit using... Modifying a design layer of an integrated circuit using...

1998-08-12

2001-05-01

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06226781

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to a proximity correction in which the layout design of an integrated circuit layer is modified by spatial definition using the layout designs of underlying and overlying integrated circuit layers.
2. Description of the Related Art
Modern integrated circuits contain numerous structures or features, typically the size of a few microns. The features are placed in localized areas, and are either conductive, non-conductive or semi-conductive (i.e., rendered conductive in defined areas with dopants). A technique known as “lithography” is used to place such features. Lithography entails using radiation to pattern a photosensitive film. An optical image is transferred to the film from a patterned mask plate (i.e., reticle) placed in proximity to the film. The photosensitive film, i.e., “photoresist”, has two main properties. First, solubility of the resist changes in response to it being exposed to appropriate radiation. Second, a hardened resist is resistant to attack by an etchant capable of removing selectively exposed conductive and/or insulative material.
According to a sequence of lithographic steps, the resist is first applied to a semiconductor topography. Next, a partially transparent mask plate is placed in close proximity to the resist. Patterns upon the mask plate are projected upon the topography using various forms of radiation. While ultraviolet light is the primary form of radiation being used, x-rays and electrons beams are growing in popularity. The radiation is transmitted through only the transparent portions of the mask plate to the resist film. The solubility of regions of the resist exposed to the radiation is altered by a photochemical reaction. The selectively exposed resist is then washed with a solvent that preferentially removes the resist areas of higher solubility. The now patterned resist is exposed to an etchant that removes those portions of the underlying topography unprotected (i.e., not covered) by the resist. Finally, the resist film is removed, leaving a duplicate of the mask plate pattern etched into a layer of the topography.
The layout design of each layer of an integrated circuit is typically generated using a computer-aided design program (“CAD”). The layout design may be replicated upon a quartz mask plate by etching the computer generated pattern into a metallic layer formed upon the mask plate. An exposure tool, e.g., a “stepper” apparatus, may be used to project the mask plate pattern onto the resist film during lithography. Most CAD programs follow a set of predetermined design rules set by processing and design limitations. For example, design rules define the minimum spacing between features of an integrated circuit layer to ensure the features are isolated from each other. Unfortunately, as integrated circuit speed and complexity continues to increase, the so-called “critical dimensions” of a circuit approach the resolution limit of the optical exposure tool. A critical dimension of an integrated circuit is the minimum feature size or the minimum spacing between features of the circuit. The resolution of an exposure tool describes its ability to distinguish closely spaced objects.
As the critical dimensions of the circuit layout approach the resolution limit of the exposure tool, the correspondence between the mask plate pattern and the pattern produced in the resist layer is significantly reduced. The degree of difference between the mask plate pattern and the resist pattern depends on the proximity of the circuit features to each other. Accordingly, the problems associated with transferring the mask plate pattern to the resist layer are referred to as “proximity effects”. The occurrence of proximity effects may be largely due to the fact that the closer the features of the mask plate pattern, the more likely the radiation waves passing through the transparent regions of the mask plate are to interact. Moreover, pre-existing layers in a semiconductor topography may reflect the radiation waves. The interacting radiation waves may thus experience diffraction and reflection effects that cause the mask plate pattern to be incorrectly printed onto the resist layer. For example, sharp comers in the mask pattern may be printed as rounded corners in the resist layer. Further, the length of a feature printed in the resist layer may be shorter than the analogous feature in the mask plate pattern.
In addition to being distorted, the features patterned in the resist layer may also be misaligned relative to the features already patterned in the semiconductor topography. Unfortunately, absent proper alignment of successive layers of an integrated circuit to each other, the operability of the integrated circuit may be at risk. In the extreme, lithographic misalignment may lead to shorting between structures that should be isolated from each other and isolation of structures that should be coupled to each other. Even if the extreme scenario does not occur, the contact resistance between successive layers of conductors in an integrated circuit, if misaligned, may be significantly increased.
To compensate for the distortions occurring in the mask plate pattern as it is transferred to the resist layer, a technique known as optical proximity correction (“OPC”) is commonly used. OPC involves biasing the layout design of an integrated circuit layer to make the pattern printed in the resist layer more like that of the original layout design. For example, a layout design may be altered to include square shaped features known as “serifs” protruding from the corner regions of the design. The presence of the serifs causes the pattern projected onto the resist layer to have sharp, rather than round corner regions. Conventional OPC techniques thus are used to achieve a desired optical appearance without being concerned with the electrical properties of the integrated circuit. However, it is not the optical appearance of the integrated circuit that allows the circuit to perform properly. Instead, it is the electrical characteristics of the integrated circuit features that determine performance. Therefore, an integrated circuit may appear to be formed according to plan even though it might function improperly.
Globally or selectively sizing features of a design layer is a common OPC technique. The features are typically enlarged to ensure that elements in different levels of an integrated circuit overlap each other by a sufficient amount, despite being misaligned. However, OPC does not take into account the design of other integrated circuit levels. The OPC only considers the proximity of features within a unitary design layer relative to each other. See, for example,
FIGS. 1-3
.
FIG. 1
illustrates a layout design of an integrated circuit. The layout design includes features
10
and
14
which represent active areas in one level of an integrated circuit. Features
12
and
16
which represent gate conductors are positioned in the design layer above respective features
10
and
14
. Further, features
18
which represent local interconnects extend above and between active features
10
and
14
. Also, features
20
which represent contacts
20
are positioned above features
12
,
16
, and
18
. As shown in
FIG. 2
, features
20
are enlarged by the same amount in all directions, regardless of the positions of the features arranged in design layers beneath features
20
.
FIG. 3
illustrates a top plan view of an integrated circuit formed according to the layout design depicted in FIG.
1
and the correction to the layout design depicted in FIG.
2
. Contacts
20
are mis-aligned relative to gate conductors
12
and
16
and local interconnects
18
. The contacts
20
residing above local interconnects
18
may come in contact with active area
10
as a result of being mis-aligned. As such, mis-aligned contacts
20
may undesirably short together active area
10
and local interconnect
18
. Therefore, globally increasing the

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