Modified locus isolation process in which surface topology of th

Details Modified locus isolation process in which surface topology of th Modified locus isolation process in which surface topology of th

1995-12-04

1997-09-30

Fourson, George

Fishing, trapping, and vermin destroying

437947, H01L 2176

Patent

active

056725388

ABSTRACT:
A method for improving the surface topology silicon wafers during the fabrication of integrated circuits is described. Regions of silicon oxide isolation, incorporated into the silicon surface by thermal oxidation, frequently present an undesirable surface topology consisting of raised regions around their perimeter. These protrusions undermine the integrity of metallization lines subsequently deposited over them. Specifically, the metal lines tend to be thinner over the surface protrusions and consequently incur high failure rates. After the isolation regions are incorporated, a silicon oxide layer is deposited which is then etched back using a unidirectional anisotropic etching step which leaves behind portions of the layer in the regions of the steepest surface gradients. This results in smoothing out the irregularities and consequently provides for more uniform and reliable metallization lines.

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