Modified LOCOS process for sub-half-micron technology

Details Modified LOCOS process for sub-half-micron technology Modified LOCOS process for sub-half-micron technology

1996-02-27

1998-05-26

Fourson, George R.

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Recessed oxide by localized oxidation

438693, H01L 2176

Patent

active

057563900

ABSTRACT:
A process for producing a wafer comprising depositing a pad oxide layer, depositing a silicon nitride layer, patterning and etching the silicon nitride to expose the wafer and define masking stacks, forming field oxide isolation regions in the exposed regions and then removing the masking stack in such a way that reduction in the thickness of the field isolation regions are minimized. In particular, in one implementation, the cap oxide on the top of the masking stack is removed through chemical mechanical polishing (CMP). In another implementation, a sacrificial passivation layer, such as silicon dioxide or polysilicon, is deposited over the field isolation regions and the masking stacks. The sacrificial passivation layer and the cap oxide on the upper surface of the masking stacks are then removed through either CMP or selective etching. With the passivation layer, the field isolation regions are protected against diminishment during subsequent etching of the cap oxide which permits the field isolation region to be initially grown to their desired thickness. This results is less bird's beak encroachment and problems associated therewith as the field isolation regions need not be as thick initially. The sacrificial passivation layer can then be removed, subsequent to removal of the masking stack by growing a sacrificial layer which either absorbs the passivation layer, or does not significantly increase its thickness, and then etching the sacrificial layer to expose the underlying wafer and isolation regions.

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