Modified L1/L2 cache inclusion for aggressive prefetch

Details Modified L1/L2 cache inclusion for aggressive prefetch Modified L1/L2 cache inclusion for aggressive prefetch

1995-08-23

1998-04-14

Kim, Matthew M.

395449, G06F 1208

Patent

active

057403996

ABSTRACT:
Within a data processing system implementing L1 and L2 caches and stream filters and buffers, prefetching of cache lines is performed in a progressive manner. In one mode, data may not be prefetched. In a second mode, two cache lines are prefetched wherein one line is prefetched into the L1 cache and the next line is prefetched into a stream buffer. In a third mode, more than two cache lines are prefetched at a time. In the third mode cache lines may be prefetched to the L1 cache and not the L2 cache, resulting in no inclusion between the L1 and L2 caches.

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