Modified glitch latch for use with power saving dynamic...

Electrical computers and digital processing systems: support – Clock control of data processing system – component – or data...

Reexamination Certificate

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C713S500000, C713S502000, C713S503000, C713S600000, C712S216000, C712S218000, C365S195000, C365S196000, C365S233100

Reexamination Certificate

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06981169

ABSTRACT:
In the Retirement Payload Array (RPA) of a microprocessor, the signal “READ” is logically combined with the primary clock signal “CLK” in a control circuit of a modified glitch latch such that the glitch latch will only reset, and therefore a reset edge or “glitch” will only appear, when new data is read and the signal IN will return to zero and allow the modified glitch latch to recover.

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Steven Wallace et al.; Title: “Design and Implementation of a 100 Mhz Reorder Buffer” IEEE 1995, -07803-2428-5/95.

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