Modified adder tree structure and method using logic and gates t

Details Modified adder tree structure and method using logic and gates t Modified adder tree structure and method using logic and gates t

1999-06-24

2000-10-03

Nguyen, Tan T.

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

326 53, 327361, H03K 19173

Patent

active

061278424

ABSTRACT:
In accordance with the present invention, an adder tree structure includes at least two adder stages. In the circuit and method according to the present invention, the first of the two adder stages generates two bits of a common weight and other more significant bits of a weight one bit more significant than the two bits of the common weight. The second of the two adder stages includes an adder that receives the more significant bits generated in the first of the two adder stages. The second adder stage also includes an AND gate which receives and logically AND's the two bits of the common weight to generate a carry-in bit for the adder in the second stage. The above adder tree structure and adding method have an advantage of permitting more input terminals of adders to contain information about the input values to the adder tree structure. Therefore, the adders are used more efficiently and less adders are required to perform a specific function.

REFERENCES:
patent: 5539332 (1996-07-01), Schmookler
patent: 5818255 (1998-10-01), New et al.

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