Semiconductor device manufacturing: process – Chemical etching – Liquid phase etching
Reexamination Certificate
1999-08-18
2002-02-19
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Liquid phase etching
C438S756000, C438S757000
Reexamination Certificate
active
06348419
ABSTRACT:
BACKGROUND
1. Technical Field
This disclosure relates to semiconductor fabrication and more particularly, to a method for reducing an etch rate of deposited layers for semiconductor devices.
2. Description of the Related Art
Semiconductor processes typically employ deposition processes and etching process to introduce and remove materials. In many instances, these processes may be employed without disrupting other structures or components previously formed. In other instances, protective layers are patterned to protect previously formed components from, for example, etching processes which may damage the previously formed components. These protective layers or blocking layers are employed in silicided junction formation for logic devices. The blocking layers prevent silicide formation on devices such as resistors which would be negatively affected by the deposition of a silicide thereon. Other applications include protection of devices or components from electrostatic discharge by employing the blocking layer.
Existing processes for forming blocking layers typically employ either low pressure chemical vapor deposited (LPCVD) nitride, thick plasma enhanced chemical vapor deposited (PECVD) nitride, or densified PECVD nitride, all of which experience process integration problems.
LPCVD nitride films have a high thermal budget which affects the device behavior. As is known in the art, high thermal budgets are typically not preferred for semiconductor fabrication processes as the often degrade device performance due to annealing and mass transport phenomenon.
Further, removing a thick PECVD nitride layer reduces the process margin for such things as gate to diffusion shorts in field effect transistors. This is due to etch processes which are typically applied to standard logic devices which recess spacers formed on sidewalls of the gate structure thereby reducing the insulation between the gate and the diffusion region (e.g., source or drain regions). Typically, conventional PECVD nitride films have either a fast etch rate in HF cleaning solutions or a fast deposition rate that requires a higher deposition thickness.
One attempt at addressing the fast etch rate in HF cleaning solutions and the fast deposition rate involves a densification process. There are primarily two potential drawbacks to densification of PECVD nitride to obtain a better wet etch rate. Both drawbacks are due to the large amount of H
2
in PECVD films. First, a device beneath the PECVD layer is in effect receiving a H
2
anneal during the densification. Boron diffusion through gate oxides are facilitated by H
2
annealing. This puts P-type field effect transistors (FETs) at risk for threshold voltage (Vt) shifts. Secondly, if there is excess H
2
gas evolution during the anneal, the nitride may blister or pop. This makes densification processes risky and difficult to employ.
Therefore, a need exists for a method of providing a blocking layer which resists etching without requiring densification. The blocking layer preferably includes a PECVD nitride blocking layer which is deposited with a relatively low thermal budget.
SUMMARY OF THE INVENTION
A method for adjusting an etch rate of a nitride layer, in accordance with the present invention includes, in a reaction chamber, providing a surface for depositing a nitride layer. The nitride layer is deposited on the surface by adjusting processing parameters to control an etch rate achievable for the nitride layer. The etch rate achievable results from the depositing step such that an ability to etch the nitride layer is determined by the adjustment of the process parameters. A refractive index measurement may be provided for monitoring the achievable etch rate for the nitride layer.
In other methods, the step of adjusting may include the step of adjusting a pressure in the reaction chamber. The step of adjusting may include the step of adjusting a flow rate of deposition gases. The deposition gases may include SiH
4
and NH
3
. The step of adjusting may also include the step of reducing a pressure in the reaction chamber to decrease the etch rate of the nitride layer. The deposition rate is preferably substantially maintained by reducing the pressure. The ability to etch the nitride layer may be measured by measuring an index of refraction of the nitride layer. The step of adjusting may include the step of adjusting the process parameters by employing a refractive index as feedback to provide an etch rate for the nitride layer. The step of depositing the nitride layer may include employing a plasma enhanced chemical vapor deposition process.
A method for adjusting an etch rate of a blocking layer in semiconductor fabrication processes includes, in a reaction chamber, providing a semiconductor device having components formed thereon, a portion of the components needing protection by a blocking layer. The blocking layer is deposited on the semiconductor device by plasma enhanced chemical vapor deposition of nitride. A pressure in the reaction chamber is adjusted for the depositing step to control an etch rate achievable for the nitride such that an ability to etch the nitride is determined by the magnitude of the pressure during the depositing step.
In other methods, the step of adjusting may include the step of adjusting a flow rate of deposition gases. The deposition gases may include at least one of SiH
4
and NH
3
. The step of adjusting may include the step of reducing a pressure in the reaction chamber to decrease the etch rate achievable for the nitride. The deposition rate is preferably substantially maintained by reducing the pressure. The etch rate achievable for the nitride may be measured by measuring an index of refraction of the nitride. The step of adjusting includes the step of adjusting the pressure by employing a refractive index as feedback to provide an achievable etch rate for the nitride may be included.
The method may further includes the step of removing the blocking layer from portions of the semiconductor device other than from the portion of the components needing protection by the blocking layer. The method may also include cleaning the semiconductor device by wet etching such that the nitride is etched at the etch rate provided during the deposition step. The wet etching may include employing at least one of HF, diluted HF and buffered HF. The step of siliciding the semiconductor device in portions other than the portion of the components needing protection by the blocking layer is also included.
Another method for adjusting an etch rate of a deposited layer, includes, in a reaction chamber, providing a surface for depositing a layer, depositing the layer on the surface, and adjusting processing parameters for the depositing step to control an achievable etch rate for the layer by measuring a refractive index of the layer such that an ability to etch the layer is determined by the adjusting of the process parameters in accordance with the refractive index.
In other methods, the step of adjusting may include the step of adjusting a pressure in the reaction chamber, and/or adjusting a flow rate of deposition gases. The deposition gases may include at least one of SiH
4
and NH
3
. The step of adjusting may include the step of reducing a pressure in the reaction chamber to decrease the etch rate of the layer. The deposition rate may be substantially maintained by reducing the pressure. The layer may include nitride. The nitride layer is preferably deposited by a plasma enhanced chemical vapor deposition process.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
REFERENCES:
patent: 4563367 (1986-01-01), Sherman
patent: 5134092 (1992-07-01), Matsumoto et al.
patent: 5468689 (1995-11-01), Cunningham et al.
patent: 5539154 (1996-07-01), Nguyen et al.
Batt Emmanuel
Grellner Frank
Jamison Paul C.
Miles Glen L.
Mosher David C.
Infineon - Technologies AG
Tran Binh X.
Utech Benjamin L.
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