Modification of carrier mobility in a semiconductor device

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Responsive to non-optical – non-electrical signal

Reexamination Certificate

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C257S018000, C257S019000, C257S108000, C257S222000, C257S417000, C257S418000, C257S747000, C438S050000, C438S051000, C438S052000, C438S053000

Reexamination Certificate

active

06943391

ABSTRACT:
Tensile or compressive stress may be added in one or more selected locations to the biaxial residual stress existing in the channel of a semiconductor device, such as a MOSFET. The periphery of the active area containing the channel is modified by following layout procedures that result in forming outward protrusions of or inward depressions in the periphery of the active area and its surrounding shallow trench isolation during generally otherwise conventional fabrication of the device.

REFERENCES:
patent: 5471073 (1995-11-01), Kohno
patent: 2003/0162348 (2003-08-01), Yeo et al.
Rim, K., et al., “Fabrication and Analysis of Deep Submicron Strained-Si N-MOSFET's,” IEEE Transactions on Electron Devices, vol. 47, No. 7, pp. 1406-1415, Jul. 2000.
Rim, K., “Strained Si Surface Channel MOSFETS for High-Performance CMOS Technology,” IEEE International Solid-State Circuits Conference, paper #7.3, pp. 116-117, 2001.
Yeo, Y.C., et al., “Enhanced performance in Sub-100 nm CMOSFETs using Strained Epitaxial Silicon-Germanium,” International Electron Device Mettings, pp. 753-756, 2000.
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Ito, S., et al., “Mechanical Stress Effect of Etch-Stop Nitride and Its Impact on Deep Submicron Transistor Design,” International Electron Device Meetings, pp. 247-250, 2000.
Shimizu, A., et al., “Local Mechanical-Stress Control (LMC): A New Technique for CMOS-Performance Enhancement,” International Electron Device Meetings, pp. 433-436, 2001.
Ota, K., et al., “Novel Locally Strained Channel Technique for High Performance 55nm CMOS,” International Electron Device Meetings, pp. 27-30, 2002.
Scott, G., et al., “NMOS Drive Current Reduction Caused by Transistor Layout and Trench Isolation Induced Stress,” International Electron Device Meetings, pp. 827-830, 1999.
Bianchi, R.A., et al., “Accurate Modeling of Trench Isolation Induced Mechanical Stress Effects on MOSFET Electrical Performance,” International Electron Device Meetings, pp. 117-120, 2002.

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