Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output process timing
Reexamination Certificate
2006-11-28
2006-11-28
Peyton, Tammara (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output process timing
C375S222000, C709S229000, C709S233000
Reexamination Certificate
active
07143212
ABSTRACT:
A modem architecture and a method of reducing on-chip memory requirements in a downloadable modem architecture are provided. The preferred architecture consists of a Digital Signal Processor (DSP) (6) with on-chip Random Access Memory (RAM) (12). A procedure which exploits inactivity intervals in a modem modulation function is provided. The procedure dynamically downloads the requisite code segments for each phase of the function from a cheaper, slower external memory (14) into the DSP on-chip RAM during inactivity intervals, thereby reducing the DSP on-chip RAM requirements.
REFERENCES:
patent: 6570911 (2003-05-01), O'Mahony
patent: 0 772 370 (1997-05-01), None
Ho, W. et al., “An Approach to Genuine Dynamic Linking,”Software Practice&Experience, 21(4)375-390, Oct. 19, 1990.
Da Costa Godfrey
Leong Foo Yuen
Pai Pratima
Iannucci Robert
Jorgenson Lisa K.
Peyton Tammara
Seed IP Law Group PLLC
STMicroelectronics Asia Pacific (PTE) Ltd.
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