Modeling interconnected propagation delay for an integrated...

Details Modeling interconnected propagation delay for an integrated... Modeling interconnected propagation delay for an integrated...

2007-05-01

2007-05-01

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C703S001000, C703S002000, C703S013000

Reexamination Certificate

active

10827791

ABSTRACT:
A system and a method are disclosed for performing a timing or signal propagation delay analysis on a circuit. The disclosure includes representing a drive logic stage as a representative linear circuit driven by a current source. The current source is represented as a function of a current at a constant value, a start time, a tail-start time, and a time constant of an equivalent capacitive circuit. Once the current source model is constructed, a logic stage can be analyzed for timing or signal propagation delay using conventional linear circuit analysis techniques. The disclosure also is applicable to resistance capacitance (“RC”) interconnect circuits using a current source model in which an RC load is represented as an effective capacitance and the current source for use in a linear analysis is constructed using an iterative approach.

REFERENCES:
patent: 5381345 (1995-01-01), Takegami et al.
patent: 5559715 (1996-09-01), Misheloff
patent: 6041170 (2000-03-01), Feldmann et al.
patent: 6314546 (2001-11-01), Muddu
patent: 6701497 (2004-03-01), Ohkubo
patent: 6807520 (2004-10-01), Zhou et al.
patent: 2004/0073418 (2004-04-01), Nassif
Barnard N. Sheehan, Library Compatible Ceff for Gate-Level Timing,2002, IEEE.
Chatzigeorgiou et al., Modeling CMOS Gates Driving RC Interconnect Loads, Apr. 2001, IEEE, vol. 48, No. 4, p. 413-418.
Choi et al., A Simple CMOS Delay Model for Wide Applications, Nov. 1996, IEEE, p. 77-80.
“SPIDER: Simultaneous Post-Layout IR-Drop and Metal Density Enhancement with Redundant Fill,” ICCAD '05, Nov. 6-10, 2005, 6 pages, San Jose, CA.
Mustafa Celik, Lawrence Pileggi, and Alan Odabasioglu, “IC Interconnect Analysis,” Chapter 8: Interfacing Interconnect and Gate-Delay Models, Jul. 2002, pp. 271-306, Kluwer Academic Publishers.
Florentin Dartu, Noel Menezes, and Lawrence T. Pileggi, “Performance Computation for Precharacterized CMOS Gates with RC Loads,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 15, No. 5, May 1996, pp. 544-553.
Richard Goering, “Synopsys Strengthens Liberty Library Format,” EEdesign, [online], Retrieved on Feb. 3, 2004, Retrieved from: <http://www.eedesign.com/article/showarticle.jhtml?articleID=17406511>.

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