Modeling a mixed-language mixed-signal design

Details Modeling a mixed-language mixed-signal design Modeling a mixed-language mixed-signal design

2007-08-21

2007-08-21

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

11126497

ABSTRACT:
A method for modeling a mixed-language and mixed-signal (MLMS) design is disclosed. The method includes receiving an MLMS design comprising at least a digital driver, a digital receiver, and an analog block connected by an MLMS net in a hierarchical structure and identifying analog-digital boundaries of the MLMS design. For each analog-digital boundary, the method further includes a) selecting a connect module (CM) by using a predetermined discipline resolution procedure; b) determining input driving values of the CM; and c) connecting the digital driver, the digital receiver, and the analog block to the CM. The method repeats steps a), b), and c) on all analog-digital boundaries of the MLMS design.

REFERENCES:
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Accellera, (Jan. 20, 2003). “Analog&Mixed-Signal Extensions to Verilog HDL”, Accellera Verilog-AMS Language Reference Manual, v.2.1, Table of Contents only, pp. v-xiv.
IEEE Standard, (Mar. 18, 1999). “IEEE Standard VHDL Analog and Mixed-Signal Extensions”, IEEE Standard 1076.1-1999, Design Automation Standards Committee of the IEEE Computer Society, Approved Mar. 18, 1999, Table of Contents only, pp. viii-x.

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