Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-10-31
2008-11-25
Whitmore, Stacy A (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
07458059
ABSTRACT:
A memory is encoded with a model of sensitivity of a distorted layout generated by simulation of a wafer fabrication process, with respect to a change in an original layout that is input to the simulation. The sensitivity model comprises an expression of convolution of the original layout with spatial functions (“kernels”) that are identical to kernels of a process model used in the simulation. A difference between the distorted layout and the original layout is computed, and the difference is divided by a sensitivity value which is obtained directly by evaluating the kemel-based sensitivity model, and the result is used to identify a proximity correction (such as serif size or contour movement) to be made to the original layout. Use of a sensitivity model based on a process model's kernels eliminates a second application of the process model to evaluate sensitivity, thereby to reduce memory and computation requirements.
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Cranford Micheal D.
Stirniman John P.
Silicon Valley Patent & Group LLP
Suryadevara Omkar
SYNOPSYS, Inc.
Whitmore Stacy A
LandOfFree
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