Model for taking into account gate resistance induced propagatio

Details Model for taking into account gate resistance induced propagatio Model for taking into account gate resistance induced propagatio

1997-07-24

2000-08-29

Lintz, Paul R.

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

703 19, 703 13, 703 14, 703 15, G06F 1750

Patent

active

061102199

ABSTRACT:
When simulating a circuit's behavior, a transistor can be modeled to account for gate resistance induced propagation delay. In one embodiment, the model includes a transistor with a resistor connected to the gate of the transistor. The resistor has a resistance equal to one third of the gate resistance.

REFERENCES:
patent: 4959565 (1990-09-01), Knetch et al.
patent: 5461579 (1995-10-01), Misheloff et al.
patent: 5553008 (1996-09-01), Huang et al.
patent: 5636130 (1997-06-01), Salem et al.
patent: 5694052 (1997-12-01), Sawai et al.
Deschacht, Denis et al. Delay Propagation Effect in Transistor Gates, IEEE Journal of Solid-State Circuits, vol. 31, No. 8, Aug. 1996, pp. 1184-1189.
Fujii, Kunihiro et al., Sub-Quarter Micron Titanium Salicide Technology with In-Situ Silicidation Using High-Temperature Sputtering, Symposium of VLSI Technology Digest of Technical Papers, 1995, pp. 57-58.
Sakurai, Takayasu, Closed-Form Expressions for Interconnections Delay, Coupling, and Crosstalk in VLSI's, IEEE Transactions of Electron Devices, vol. 40, No. 1, Jan. 1993, pp. 118-124.
Takagi, M.T. et al, A Novel 0.15 .mu.m CMOS Technology using W/WNx/Polysilicon Gate Electrode and Ti Silicided Source/Drain Diffusions, IEDM 1996, pp. 455-458.

Affiliated with

Also associated with

Rating

Model for taking into account gate resistance induced propagatio does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Model for taking into account gate resistance induced propagatio, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Model for taking into account gate resistance induced propagatio will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1244761