Model checking with layered localization reduction

Details Model checking with layered localization reduction Model checking with layered localization reduction

2005-10-18

2005-10-18

Thompson, A. M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C703S014000

Reexamination Certificate

active

06957404

ABSTRACT:
A method for verifying a property of a complete model of a system under study includes abstracting at least some of the variables from the model so as to produce an abstract model of the system. Beginning with an initial state in a state space of the abstract model, an abstract path is found through the state space of the abstract model in accordance with the transition relation to a target state defined by the property. A subset of the abstracted variables is restored to the abstract model so as to produce an intermediate model of the system, and the property on the complete model is verified based on the intermediate model.

REFERENCES:
patent: 6484134 (2002-11-01), Hoskote
patent: 6591400 (2003-07-01), Yang
patent: 6643827 (2003-11-01), Yang
patent: 6725431 (2004-04-01), Yang
patent: 2002/0144236 (2002-10-01), Beer et al.
patent: 2003/0208732 (2003-11-01), Yang
Mir et al., “Modeling and verification of embedded systems using Cadence SMV”, Mar. 7-10, 2000, Electrical and Computer Engineering, 2000 Canadian Conference on , vol.: 1, pp.: 179-183 vol. 1.
Vakilotojar et al., “RTL verification of timed asynchronous and heterogeneous systems using symbolic model checking”, Jan. 28-31, 1997, Design Automation Conference 1997. Proceedings of the ASP-DAC '97. Asia and South Pacific, pp.: 181-188.
Yunja et al., “Model checking software requirement specifications using domain reduction abstraction”, Oct. 6-10, 2003, Automated Software Engineering, 2003. Proceedings. 18th IEEE International Conference on , pp.: 314-317.
Ammann et al., “Abstracting formal specifications to generate software tests via model checking”, Oct. 24-29, 1999, Digital Avionics Systems Conference, 1999. Proceedings. 18th , vol.: 2, pp.: 10.A.6-1—10.A6-10 vol. 2.
Kamhi et al., “Adaptive variable reordering for symbolic model checking”, Nov. 8-12, 1998, Computer-Aided Design, 1998. ICCAD 98. Digest of Technical Papers. 1998 IEEE/ACM International Conference on , Nov. 8-12, 1998, pp.: 359-365.
Sreemani et al., “Feasibility of model checking software requirements: a case study”, Jun. 17-21, 1996, Computer Assurance, 1996. COMPASS '96, ‘Systems Integrity. Software Safety. Process Security’. Proceedings of the Eleventh Annual Conference, pp.: 77-88.
E. Clarke, O. Grumberg, S. Jha, Y. Lu, H. Veith, ‘Counterexample-guided Abstraction Refinement,’ In Proc. ComputerAided Verif., pp. 154-169, Jul. 2000.
E.M. Clarke, O. Grumberg and D.A.I Peled, “Model Checking”, MIT Press, pp. 171-180, Dec. 1999.

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