Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-09-08
2009-12-01
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07627837
ABSTRACT:
A system and method are provided for analyzing layout patterns via simulation using a lithography model to characterize the patterns and generate rules to be used in rule-based optical proximity correction (OPC). The system and method analyze a series of layout patterns conforming to a set of design rules by simulation using a lithography model to obtain a partition of the pattern spaces into one portion that requires only rule-based OPC and another portion that requires model-based OPC. A corresponding hybrid OPC system and method are also introduced that utilize the generated rules to correct an integrated circuit (IC) design layout which reduces the OPC output complexity and improves turnaround time.
REFERENCES:
patent: 2003/0097647 (2003-05-01), Pierrat et al.
patent: 2003/0149955 (2003-08-01), Ohnuma
patent: 2005/0044513 (2005-02-01), Robles et al.
Chiang Jack
Estill Hall
Memula Suresh
Milks, III William C.
Takumi Technology Corp.
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