Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-08-15
2006-08-15
Whitmore, Stacy A. (Department: 2812)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
07093224
ABSTRACT:
A technique for designing a logic circuit includes specifying a model. The model including combinatorial blocks, state elements and graphical library elements. The technique maintains a data structure representative of the model, and generates an architectural model and an implementation model from the data structure. The data structure represents a descriptive net list of the model. The architectural model includes C++ code and the implementation model includes Verilog.
REFERENCES:
patent: 4703435 (1987-10-01), Darringer et al.
patent: 4970664 (1990-11-01), Kaiser et al.
patent: 5128871 (1992-07-01), Schmitz
patent: 5212650 (1993-05-01), Hooper et al.
patent: 5220512 (1993-06-01), Watkins et al.
patent: 5258919 (1993-11-01), Yamanouchi et al.
patent: 5267175 (1993-11-01), Hooper
patent: 5278769 (1994-01-01), Bair et al.
patent: 5287289 (1994-02-01), Kageyama et al.
patent: 5297053 (1994-03-01), Pease et al.
patent: 5301318 (1994-04-01), Mittal
patent: 5384710 (1995-01-01), Lam et al.
patent: 5475605 (1995-12-01), Lin
patent: 5493507 (1996-02-01), Shinde et al.
patent: 5506788 (1996-04-01), Cheng et al.
patent: 5513119 (1996-04-01), Moore et al.
patent: 5544067 (1996-08-01), Rostoker et al.
patent: 5553002 (1996-09-01), Dangelo et al.
patent: 5568397 (1996-10-01), Yamashita et al.
patent: 5598347 (1997-01-01), Iwasaki
patent: 5603015 (1997-02-01), Kurosawa et al.
patent: 5604894 (1997-02-01), Pickens et al.
patent: 5629857 (1997-05-01), Brennan
patent: 5663662 (1997-09-01), Kurosawa
patent: 5666289 (1997-09-01), Watkins
patent: 5673198 (1997-09-01), Lawman et al.
patent: 5685006 (1997-11-01), Shiraishi
patent: 5694579 (1997-12-01), Razdan et al.
patent: 5706476 (1998-01-01), Giramma
patent: 5717928 (1998-02-01), Campmas et al.
patent: 5724250 (1998-03-01), Kerzman et al.
patent: 5757655 (1998-05-01), Shih et al.
patent: 5809283 (1998-09-01), Vaidyanathan et al.
patent: 5828581 (1998-10-01), Matumura
patent: 5831869 (1998-11-01), Ellis et al.
patent: 5841663 (1998-11-01), Sharma et al.
patent: 5852564 (1998-12-01), King et al.
patent: 5889677 (1999-03-01), Yasuda et al.
patent: 5892678 (1999-04-01), Tokunoh et al.
patent: 5892682 (1999-04-01), Hasley et al.
patent: 5903469 (1999-05-01), Ho
patent: 5933356 (1999-08-01), Rostoker et al.
patent: 5937190 (1999-08-01), Gregory et al.
patent: 5963724 (1999-10-01), Mantooth et al.
patent: 5974242 (1999-10-01), Damarla et al.
patent: 6044211 (2000-03-01), Jain
patent: 6053947 (2000-04-01), Parson
patent: 6066179 (2000-05-01), Allan
patent: 6077304 (2000-06-01), Kasuya
patent: 6106568 (2000-08-01), Beausang et al.
patent: 6117183 (2000-09-01), Teranishi et al.
patent: 6120549 (2000-09-01), Goslin et al.
patent: 6132109 (2000-10-01), Gregory et al.
patent: 6135647 (2000-10-01), Balakrishnan et al.
patent: 6152612 (2000-11-01), Liao et al.
patent: 6161211 (2000-12-01), Southgate
patent: 6178541 (2001-01-01), Joly et al.
patent: 6205573 (2001-03-01), Hasegawa
patent: 6208954 (2001-03-01), Houtchens
patent: 6216256 (2001-04-01), Inoue et al.
patent: 6219822 (2001-04-01), Griestede et al.
patent: 6226780 (2001-05-01), Bahra et al.
patent: 6233540 (2001-05-01), Schaumont et al.
patent: 6233723 (2001-05-01), Pribetich
patent: 6234658 (2001-05-01), Houldsworth
patent: 6236956 (2001-05-01), Mantooth et al.
patent: 6260179 (2001-07-01), Ohsawa et al.
patent: 6272671 (2001-08-01), Fakhry
patent: 6275973 (2001-08-01), Wein
patent: 6292931 (2001-09-01), Dupenloup
patent: 6298468 (2001-10-01), Zhen
patent: 6311309 (2001-10-01), Southgate
patent: 6324678 (2001-11-01), Dangelo et al.
patent: 6327693 (2001-12-01), Cheng et al.
patent: 6353806 (2002-03-01), Gehlot
patent: 6353915 (2002-03-01), Deal et al.
patent: 6360356 (2002-03-01), Eng
patent: 6366874 (2002-04-01), Lee et al.
patent: 6378115 (2002-04-01), Sakurai
patent: 6381563 (2002-04-01), O'Riordan et al.
patent: 6381565 (2002-04-01), Nakamura
patent: 6401230 (2002-06-01), Ahanessians et al.
patent: 6421816 (2002-07-01), Ishikura
patent: 6438729 (2002-08-01), Ho
patent: 6438731 (2002-08-01), Segal
patent: 6440780 (2002-08-01), Kimura et al.
patent: 6449762 (2002-09-01), McElvain
patent: 6457164 (2002-09-01), Hwang et al.
patent: 6473885 (2002-10-01), Wallace
patent: 6477683 (2002-11-01), Killian et al.
patent: 6477688 (2002-11-01), Wallace
patent: 6477689 (2002-11-01), Mandell et al.
patent: 6480985 (2002-11-01), Reynolds et al.
patent: 6487698 (2002-11-01), Andreev et al.
patent: 6490545 (2002-12-01), Peng
patent: 6505328 (2003-01-01), Van Ginneken et al.
patent: 6505341 (2003-01-01), Harris et al.
patent: 6516456 (2003-02-01), Garnett et al.
patent: 6519742 (2003-02-01), Falk
patent: 6519755 (2003-02-01), Anderson
patent: 6523156 (2003-02-01), Cirit
patent: 6539536 (2003-03-01), Singh et al.
patent: RE38059 (2003-04-01), Yano et al.
patent: 6546528 (2003-04-01), Sasaki et al.
patent: 6574787 (2003-06-01), Anderson
patent: 6591407 (2003-07-01), Kaufman et al.
patent: 2001/0018758 (2001-08-01), Tanaka et al.
patent: 2002/0023256 (2002-02-01), Seawright
patent: 2002/0038447 (2002-03-01), Kim et al.
patent: 2002/0042904 (2002-04-01), Ito et al.
patent: 2002/0046386 (2002-04-01), Skoll et al.
patent: 2002/0049957 (2002-04-01), Hosono et al.
patent: 2002/0059054 (2002-05-01), Bade et al.
patent: 2002/0112221 (2002-08-01), Ferreri et al.
patent: 2002/0138244 (2002-09-01), Meyer
patent: 2002/0166100 (2002-11-01), Meding
patent: 2003/0004699 (2003-01-01), Choi et al.
patent: 2003/0005396 (2003-01-01), Chen et al.
patent: 2003/0016206 (2003-01-01), Taitel
patent: 2003/0016246 (2003-01-01), Singh
patent: 2003/0036871 (2003-02-01), Fuller et al.
patent: 2003/0177455 (2003-09-01), Kaufman et al.
patent: 0 404 482 (1990-12-01), None
patent: 0 433 066 (1991-06-01), None
patent: 0 720 233 (1996-07-01), None
patent: 0 901 088 (1999-03-01), None
patent: 1 065 611 (2001-01-01), None
patent: 58-060559 (1983-04-01), None
patent: 03-225523 (1991-10-01), None
patent: 07-049890 (1995-02-01), None
patent: 08-314892 (1996-11-01), None
patent: 2001-068994 (2001-03-01), None
patent: WO 98/37475 (1998-08-01), None
patent: WO 98/55879 (1998-12-01), None
patent: WO 99/39268 (1999-08-01), None
patent: WO00/65492 (2000-11-01), None
Gassenfeit, E. H., “Control System Design Realization via VHDL-A: Requirements”, Proceedings of the 1996 IEEE International Symposium on Computer-Aided Control System Design, Sep. 15, 1996, pp. 282-285.
Kutzschebauch, “Efficient logic optimization using regularity extraction”, Proceedings of 2000 International Conference on Computer Design, Sep. 17, 2000, pp. 487-493.
Lahti, et al., “SADE: a Graphical Toll for VHDL-Based System Analysis”, 1991 IEEE International Conference on Computer-Aided Design, Nov. 11, 1991, pp. 262-265.
Lin, et al., “A Goal Tree Based High-Level Test Planning System for DSP Real Number Models”, 1998 Proceedings of International Test Conference, Oct. 18, 1998, pp. 1000-1009.
Maxfield, C., “Digital Logic Simulation: Event-Driven, Cycle-Based, and Home-Brewed”,Electrical Design News,41(14):129-136 (1996).
NB84035598, “Binary Relational Schema to Model Structured LSI Design”, IBM Technical Disclosure Bulletin, vol. 26, No. 10B, Mar. 1984, pp. 5598-5601.
NN7807629, “Functional Oriented Symbolic Macromodeling Algorithm”, IBM Technical Disclosure Bulletin, vol. 21, No. 2, Jul. 1978, pp. 629-631.
NN8006341, “Macro Physical-To-Logical Checking LSI Chip Design”, IBM Technical Disclosure Bulletin, vol. 23, No. 1, Jun. 1980, pp. 341-345.
NN9407481, “Functional Modeling using object Collaboration Diagram”, IBM Technical Disclosure Bulletin, vol. 37, No. 7, Jul. 1994, pp. 481-486.
Parlakbilek, et al., “A Multiple-Strength Multiple-Delay Compiled-Code Logic Simulator”,IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,12(12):1937-1946 (1993).
Su, Stephen, “An Interactive Design Automation System”,Proceedings of the 10th Design Automation Workshop on Design Automation,pp. 253-261, Jun. 1973.
Yli-Pietila, et al., &#
Adiletta Matthew J.
Clark Christopher
Fennel Timothy J.
Wheeler William R.
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