Mobile wireless communication device architectures and...

Details Mobile wireless communication device architectures and... Mobile wireless communication device architectures and...

2005-09-27

2005-09-27

McLean-Mayo, Kimberly (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

C711S150000, C711S154000, C711S149000

Reexamination Certificate

active

06950910

ABSTRACT:
A wireless communications architecture having first and second synchronous memory devices coupled to a virtual channel memory controller by corresponding first and second data buses, and a shared address and control bus interconnecting the virtual channel memory controller and the first and second synchronous memory devices. The first and second synchronous memory devices are addressed with the shared address bus, and the first and second memory locations are accessed via the first and second data buses, respectively.

REFERENCES:
patent: 5978866 (1999-11-01), Nain
patent: 6021077 (2000-02-01), Nakaoka
patent: 6611537 (2003-08-01), Edens et al.
patent: 2001/0053069 (2001-12-01), Haba et al.
patent: 2002/0174311 (2002-11-01), Ware et al.
patent: 2003/0105906 (2003-06-01), Zhao

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