Electrical computers and digital data processing systems: input/ – Interrupt processing
Reexamination Certificate
2001-05-10
2004-10-19
Vo, Tim (Department: 2112)
Electrical computers and digital data processing systems: input/
Interrupt processing
C710S261000, C710S262000, C710S263000, C710S264000
Reexamination Certificate
active
06807595
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to mobile communication devices such as wireless telephones configured for use within code division multiple access (CDMA) wireless systems and in particular to microprocessor systems for use therein.
2. Description of the Related Art
CDMA is a wireless communication system for processing voice or data communications. Briefly, with CDMA, digitized voice or data signals are separated into discrete packets and transmitted altogether to achieve optimal overall transmission bandwidth. Upon reception, the packs are reassembled and converted back to voice or data signals. To prepare the voice or data signals for CDMA transmission, a wireless telephone includes various dedicated hardware components for performing CDMA-specific functions. Examples include a digital signal processor (DSP) vocoder for digitizing voice signals, an encoder for encoding the signals for error detection and correction purposes, an interleaver for interleaving portions of encoded signals so as to achieve signal transmission time diversity and thereby reduce transmission power requirements, and a modulator for modulating the interleaved signals for subsequent transmission via a radio antenna. To convert received CDMA signals back into voice or data signals, the wireless telephone includes other dedicated CDMA hardware components such as a CDMA demodulator for de-modulating received radio signals, a de-interleaver for reversing the effect of interleaving, and a CDMA decoder for decoding the encoded signals to thereby extract a voice or data signal.
Within the wireless telephone, the various CDMA receive and transmit components are peripheral components operating under control of a central microprocessor. To perform their various functions, the peripheral components often must have the microprocessor to perform operations on their behalf, such as to transfer data from a central memory system to the peripheral device. If so, the peripheral component transmit an interrupt request signal to the microprocessor specifying a particular operation to be performed by the microprocessor on behalf of the peripheral device. In response to the interrupt request, the microprocessor suspends current microprocessor operations and retrieves and executes a pre-stored interrupt service routine associated with the specific interrupt request. In the case of a data retrieval interrupt request, the interrupt service routine prepares and transmits appropriate memory access signals to the memory system for retrieving the requested data and forwarding the data to the peripheral component issuing the interrupt request. Typically, a different interrupt service routine is stored for each different interrupt request that may be processed by the microprocessor.
The microprocessor periodically scans a plurality of interrupt request lines to detect interrupt requests issued by the peripheral components. Numerous interrupt requests can be received by the microprocessor over the interrupt lines at about the same time. Hence, the microprocessor includes internal components for prioritizing the requests. Microprocessor processes the highest priority interrupt signal first by retrieving and executing the interrupt service routine associated therewith. If an interrupt request having a still higher priority is then received, the microprocessor interrupts the processing of the previous interrupt request to respond to the new higher priority request. With numerous interrupt requests being received by the microprocessor, numerous interrupt service routines may need to be “nested” with the microprocessor to permit all interrupt requests to be processed ultimately. Thus, the microprocessor must not only prioritize interrupt request signals received at the same time bust must also compared the relative priority of newly received interrupt request signals with those of previously received interrupt request signals. In state of the art wireless telephones, wherein numerous peripheral components operate concurrently, numerous interrupt request signals may be received by the microprocessor within each clock cycle and, hence, the microprocessor may need to devote considerable resources to prioritizing signals. Complicated software or hardware may need to be provided, and the costs associated with designing, testing and debugging the hardware or software may add to the overall cost of the wireless telephone. Also, changes to the overall system in which the microprocessor is installed, such as changes in the overall prioritization scheme of interrupt requests within the system, may require that the interrupt request prioritization portions of the microprocessor be modified, further increasing design, debugging, and testing costs for the system. Also, if a complicated prioritization protocol needs to be performed by the microprocessor, there may be a significant delay between receipt of an interrupt request signal and execution of the interrupt service routine corresponding therewith. As a result, overall system performance may be degraded. To compensate, the clock speed of the microprocessor can be increased, but power consumption is thereby also increased, which is particularly undesirable within mobile wireless telephones.
Another problem that arises within many conventional microprocessor which include internal interrupt request prioritization hardware or software, is that considerable microprocessor resources may be required to process various nested interrupt service routines, particularly if interrupt request signals are received one after the other. Briefly, when a new interrupt request signal of high priority is received, the “context” associated with the current processing of the microprocessor is stored in context storage registers. After the new interrupt request has been fully processed, the microprocessor restores to save context and resumes processing the previous interrupt request. The process of restoring the context associated with a previous interrupt service routine is referred to as a “jump” operation. However, within state of the art systems having numerous peripheral components generating numerous interrupt request, the microprocessor may immediately receive a new interrupt request of high priority. As a result, after having just devoted resources to restoring the context associated with a lower priority request, the microprocessor must immediately re-save the context and respond to the new interrupt request. As can be appreciated, considerable processing time either results in still further delays in the initiation of interrupt service routines associated with newly received interrupt requests, or necessitates a still further increase in clock speed of the microprocessor. Hence, either overall system efficiency or overall power consumption of the wireless telephone suffers.
Yet another problem associated with many conventional microprocessors which provide internal interrupt request prioritization software or hardware, is that, to maximize power savings, the microprocessor often needs to switch to a power shut down mode wherein the microprocessor draws either reduced power or no power at all. However, upon receipt of any new interrupt request signal, the microprocessor must power up to determine the priority of the interrupt request and then determine whether the interrupt request needs to be immediately processed or whether the microprocessor can return to the power shut down mode and process the interrupt request later. Thus, even interrupt requests which do not have a sufficiently high priority to justify powering up the microprocessor will nevertheless result in the microprocessor being powered up, at least long enough to access the priority of the received interrupt request. Hence, still further power savings are lost.
Accordingly, it would be highly desirable to provide an improved microprocessor-based system for use within wireless telephones or other mobile communication devices which provides an improved system and method for processing interrupt requests a
Khan Safi
Pan Hanfang
Yu Nicholas K.
Brown Charles D.
Qualcomm Incorporated
Seo Howard H.
Vo Tim
Wadsworth Philip
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