MNOS non-volatile memory with write cycle suppression

Details MNOS non-volatile memory with write cycle suppression MNOS non-volatile memory with write cycle suppression

1976-12-29

1978-05-16

Hecker, Stuart N.

Static information storage and retrieval

Systems using particular element

Semiconductive

365195, G11C 700, G11C 1140

Patent

active

040902587

ABSTRACT:
An improved memory for storing digital data is described incorporating two variable threshold transistors per memory cell which are written in opposite directions concomitantly by applying a polarizing voltage across the gate insulator of each transistor. Subsequent writing into the memory cell is limited by means of sensing the data stored and comparing it with the data to be written to permit only write cycles where the data stored would be opposite. The variable threshold transistors are thereby operated out of saturation by shifting the voltage thresholds back and forth in opposite directions. By utilizing two variable threshold devices per memory cell, data is sensed by the difference in the conductance of the two devices providing a wider detection window.

REFERENCES:
patent: 3579204 (1971-05-01), Lincoln
patent: 3801965 (1974-04-01), Keller et al.
patent: 3836894 (1974-09-01), Cricchi
patent: 3936811 (1976-02-01), Horninger

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