MNOS FET memory retention characterization test circuit with enh

Details MNOS FET memory retention characterization test circuit with enh MNOS FET memory retention characterization test circuit with enh

1977-08-03

1978-12-19

Konick, Bernard

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

307279, 307DIG3, 307DIG4, 365184, 365227, G11C 1140, G11C 700

Patent

active

041308972

ABSTRACT:
An improved sense latch circuit for differentially sensing an MNOS memory FET's voltage thresholds, selectively operable in either a memory retention or read interrogation mode with enhanced sensitivity and improved power conservation. The improvement consisting of the additional cross coupling of each of the latch outputs to a respective plurality of MOS FETs coupled in series with each of the MNOS FET inputs, which cross coupling reduces extraneous current paths and increases the switching sensitivity of the sense latch circuit.

REFERENCES:
patent: 3579204 (1971-05-01), Lincoln
patent: 3838295 (1974-09-01), Lindell
patent: 3976895 (1976-08-01), Koo
patent: 3987315 (1976-10-01), Matsue
patent: 3993919 (1976-11-01), Cox et al.
patent: 4027176 (1977-05-01), Heuber et al.
patent: 4039861 (1977-08-01), Heller et al.

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