Mixed-voltage tolerant I/O buffer and output buffer circuit...

Details Mixed-voltage tolerant I/O buffer and output buffer circuit... Mixed-voltage tolerant I/O buffer and output buffer circuit...

2008-12-09

2010-11-23

Barnie, Rexford N (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S087000, C326S026000

Reexamination Certificate

active

07839174

ABSTRACT:
An output buffer circuit includes a high voltage detecting circuit, a dynamic gate bias generating circuit, an output stage circuit and a pad voltage detector. The high voltage detecting circuit detects a power supply voltage and generates a first and a second determining signals and a first and a second bias voltages according to the power supply voltage. The dynamic gate bias generating circuit is biased by the first and the second bias voltages and receives the first and the second determining signals, for converting logic control signals into corresponding gate bias voltages according to the first and the second determining signals. The pad voltage detector detects a voltage of an I/O pad and provides a pad voltage detecting signal for the output stage circuit to modify an output signal outputted to an I/O pad. A mixed-voltage input/output (I/O) buffer is disclosed herein.

REFERENCES:
patent: 6018267 (2000-01-01), Tran et al.
patent: 6323704 (2001-11-01), Pelley et al.
patent: 6351358 (2002-02-01), Allen
patent: 6586974 (2003-07-01), Humphrey et al.
patent: 7112996 (2006-09-01), Lee

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