Electronic digital logic circuitry – Interface – Supply voltage level shifting
Patent
1994-06-20
1995-06-13
Hudspeth, David R.
Electronic digital logic circuitry
Interface
Supply voltage level shifting
326 31, 326 58, H03K 19094
Patent
active
054246598
ABSTRACT:
A tristate buffer circuit for mixed voltage applications. The circuit is built from field effect transistors and is used as an output buffer in applications where a low voltage component needs to drive both components which are powered by the same low voltage and components which are powered by a higher voltage. The circuit uses a floating n-well technique in combination with a pass-gate network, a one-shot circuit, and a process-dependent bias voltage reference. It is particularly useful on CMOS semiconductor chips which have bus interfaces, such as local area network (LAN) protocol chips.
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Article: "A 3.3V ASIC for Mixed Voltage Applications with Shut Down Mode" CICC May 9-May 12. Makoto Ueda et al; IBM Yasu Technology Application Laboratory, Ichimiyake-800, Yasu, Shiga-ken Japan.
Toshiba Semiconductor System Engineering Center, Japan, Article: "Highly Reliable Process Insensitive 3.3V-5V Interface Circuit" Y. Wada, J. Gotoh, H. Takakura, T. Iida, T. Noguchi.
Stephens Geoffrey B.
Tucker Scott J.
Hudspeth David R.
International Business Machines Corp.
Phillips Steven B.
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