Mixed threshold voltage CMOS logic device and method of...

Details Mixed threshold voltage CMOS logic device and method of... Mixed threshold voltage CMOS logic device and method of...

2000-09-27

2002-04-09

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Threshold

With field-effect transistor

C326S119000, C326S121000, C326S098000

Reexamination Certificate

active

06369606

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This present invention relates generally to electronic circuits generally, and more specifically, to CMOS logic circuit devices and device families thereof, each circuit designed with two or more series CMOS transistor elements having different gate voltage thresholds for improved performance.
2. Discussion of the Prior Art
Chip power supply voltages are continually scaling downward as technology advances while device thresholds are remaining relatively constant. As is well known, the speed of CMOS logic gates is proportional to the square of overdrive voltage (VDD-Vt). At VDD of 2.5V and lower, the device overdrive becomes increasingly more sensitive to Vt. This sensitivity is somewhat compensated in modern processes by providing two kinds of Vt's for both NMOS and PMOS devices: 1) a “normal” Vt device that functions to limit “off current”, i.e., current when the gate is not biased, i.e. V
gate
<Vt; and, 2) a device having a Vt voltage lower than the normal Vt for improving switching performance (speed) where leakage is not critical. Schematic symbols for a normal Vt device
15
(PMOS) and normal Vt device
25
(NMOS) manufactured according to a modern CMOS process are shown in FIGS.
1
(
a
) and
1
(
b
), respectively. Schematic symbols for a low Vt device
15
′ (PMOS) and a low Vt device
25
′ (NMOS) manufactured according to a modern CMOS process are shown in FIGS.
1
(
c
) and
1
(
d
), respectively. A “classic” two input CMOS logic NAND gate
10
and two input CMOS logic NOR gate
14
both implemented with normal Vt devices
15
in accordance with the prior art is shown in FIGS.
2
(
a
) and
2
(
b
).
One typical application of a low Vt device is in a DRAM array sense amplifier operating at ½ bit line voltage (i.e. 0.8V), with only 0.3V or 0.4V overdrive beyond Vt. In this application the drain to source voltage is 0 and leakage is not a problem. In some practices, blocks of low Vt logic may be gated with a “normal” Vt device in order to control leakage.
It would thus be highly desirable to provide an individual CMOS logic gate that exhibits both improved performance and limited leakage by providing a mixed series connection comprising a low Vt CMOS device and a normal Vt CMOS device.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a logic circuit capable of exhibiting enhanced switching speed for logic operations and reduced leakage current when operating in an off-state.
It is another object of the invention to provide a logic circuit family including logic devices capable of exhibiting enhanced switching speed for logic operations and reduced leakage current when operating in an off-state.
According to one aspect of the invention, there is provided a logic circuit implementing a logic function comprising a series connection of two or more devices, at least one device having a threshold voltage at an input lower than a threshold voltage at an input of another of the devices. The logic circuit exhibits enhanced switching speed for logic operations and reduced leakage current when operating in an off-state.
According to another aspect of the invention, there is provided a method for fabricating a CMOS logic circuit comprising the steps of: a) defining an common active well region in a semiconductor material of first conductivity type where the two or more CMOS devices are to be fabricated; b) providing compensation mask to define first and second devices in the common active well region; c) altering conductivity of a second device in the active well by compensation ion implanting, the conductivity of the second device being altered to one of: raise or lower device gate the threshold voltage of the second device; d) patterning gate conductor region for the first and second devices over the common active well; and, e) overlaying separation mask and ion implanting source and drain diffusion regions for the first and second devices, wherein the CMOS logic circuit comprises a series connection of two devices, at least one device being uncompensated and having a threshold voltage at a gate input lower than a threshold voltage at a gate input of a second compensated device.


REFERENCES:
patent: 5440244 (1995-08-01), Richter et al.
patent: 5481484 (1996-01-01), Ogawa et al.
patent: 5798658 (1998-08-01), Werking
patent: 5831451 (1998-11-01), Bosshart
patent: 5982211 (1999-11-01), Ko
patent: 6111427 (2000-08-01), Fujii et al.
patent: 6133762 (2000-10-01), Hill et al.

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