Mixed mode output buffer circuit for CMOSIC

Details Mixed mode output buffer circuit for CMOSIC Mixed mode output buffer circuit for CMOSIC

1996-06-13

1997-07-08

Westin, Edward P.

Electronic digital logic circuitry

Interface

Current driving

326 34, 326 58, 326 81, 327313, H03K 190948

Patent

active

056465513

ABSTRACT:
This invention provides circuits which provide stable internally derived voltages for mixed mode large scale integrated circuits having SRAM, DRAM, and the like. The circuits use a summation of threshold voltages of metal oxide semiconductor field effect transistors to clamp voltages and a level detection circuit to compensate for variation in the primary supply voltage. A load detection and feedback circuit using a parasitic bipolar transistor provides voltage stability over a wide range of loading conditions.

REFERENCES:
patent: 4347447 (1982-08-01), Proebsting
patent: 4527077 (1985-07-01), Higuchi et al.
patent: 5248907 (1993-09-01), Lin et al.
patent: 5319256 (1994-06-01), Koyanagi et al.
patent: 5321319 (1994-06-01), Mahmood

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