Mixed mode output buffer circuit for CMOSIC

Details Mixed mode output buffer circuit for CMOSIC Mixed mode output buffer circuit for CMOSIC

1996-06-13

1997-05-27

Westin, Edward P.

Electronic digital logic circuitry

Interface

Current driving

326 34, 326 81, 326 83, 327313, H03K 190948, H03K 19082

Patent

active

056336047

ABSTRACT:
This invention provides circuits which provide stable internally derived voltages for mixed mode large scale integrated circuits having SRAM, DRAM, and the like. The circuits use a summation of threshold voltages of metal oxide semiconductor field effect transistors to clamp voltages and a level detection circuit to compensate for variation in the primary supply voltage. A load detection and feedback circuit using a parasitic bipolar transistor provides voltage stability over a wide range of loading conditions.

REFERENCES:
patent: 4746817 (1988-05-01), Banker et al.
patent: 5107142 (1992-04-01), Bhamidipaty
patent: 5355030 (1994-10-01), Buchholtz et al.
patent: 5430404 (1995-07-01), Campbell et al.

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